Ferroelectrics are promising for nonvolatile memories. However, the difficulty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system.

The multidisciplinary field of memristors calls for the necessity for theoreticallyinclined researchers and experimenters to join forces, merging complementary expertise and technical know-how, to develop and implement rigorous and systematic techniques to design variability-aware memristor-based circuits and systems. The availability of a predictive physics-based model for a memristor is a necessary requirement before commencing these investigations. An interesting dynamic phenomenon, occurring ubiquitously in non-volatile memristors, is fading memory. The latter may be defined as the appearance of a unique steady-state behavior, irrespective of the choice of the initial condition from an admissible range of values, for each stimulus from a certain family, for example, the DC or the purely-AC periodic input class. This paper first provides experimental evidence for the emergence of fading memory effects in the response of a TaOₓ redox-based random access memory cell to inputs from both of these classes. Leveraging the predictive capability of a physics-based device model, called JART VCM v1, a thorough system-theoretic analysis, revolving around the Dynamic Route Map graphic tool, is presented. This analysis allows to gain a better understanding of the mechanisms, underlying the emergence of history erase effects, and to identify the main factors, that modulate this nonlinear phenomenon, toward future potential applications.

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

En la actualidad, la Internet de las Cosas (Internet of Things, IoT) es una tecnología esencial para la próxima generación de sistemas inalámbricos. La conectividad es la base de IoT, y el tipo de acceso requerido dependerá de la naturaleza de la aplicación. Uno de los principales facilitadores del entorno IoT es la comunicación machine-to-machine (M2M) y, en particular, su enorme potencial para ofrecer conectividad ubicua entre dispositivos inteligentes. Las redes celulares son la elección natural para las aplicaciones emergentes de IoT y M2M. Un desafío importante en las redes celulares es conseguir que la red sea capaz de manejar escenarios de acceso masivo en los que numerosos dispositivos utilizan comunicaciones M2M. Por otro lado, los sistemas celulares han experimentado un tremendo desarrollo en las últimas décadas: incorporan tecnología sofisticada y nuevos algoritmos para ofrecer una amplia gama de servicios. El modelado y análisis del rendimiento de estas redes multiservicio es también una tarea desafiante que podría requerir un gran esfuerzo computacional. Para abordar los desafíos anteriores, nos centramos en primer lugar en el diseño y la evaluación de las prestaciones de nuevos mecanismos de control de acceso para hacer frente a las comunicaciones masivas M2M en redes celulares. Posteriormente nos ocupamos de la evaluación de prestaciones de redes multiservicio y proponemos una nueva técnica analítica que ofrece precisión y eficiencia computacional. Nuestro principal objetivo es proporcionar soluciones para aliviar la congestión en la red de acceso radio cuando un gran número de dispositivos M2M intentan conectarse a la red. Consideramos los siguientes tipos de escenarios: (i) los dispositivos M2M se conectan directamente a las estaciones base celulares, y (ii) forman grupos y los datos se envían a concentradores de tráfico (gateways) que les proporcionan acceso a la infraestructura. En el primer escenario, dado que el número de dispositivos añadidos a la red aumenta continuamente, esta debería ser capaz de manejar el considerable incremento en las solicitudes de acceso. El 3rd Generation Partnership Project (3GPP) ha propuesto el access class barring (ACB) como una solución práctica para el control de congestión en la red de acceso radio y la red troncal. El ajuste correcto de los parámetros de ACB de acuerdo con la intensidad del tráfico es crítico, pero cómo hacerlo de forma dinámica y autónoma es un problema complejo cuya solución no está recogida en las especificaciones del 3GPP. Esta tesis doctoral contribuye al análisis del rendimiento y al diseño de nuevos algoritmos que implementen efectivamente este mecanismo, y así superar los desafíos introducidos por las comunicaciones masivas M2M. En el segundo escenario, dado que la heterogeneidad de los dispositivos IoT y las arquitecturas celulares basadas en hardware imponen desafíos aún mayores para permitir una comunicación flexible y eficiente en los sistemas inalámbricos 5G, esta tesis doctoral también contribuye al diseño de software-defined gateways (SD-GWs) en una nueva arquitectura propuesta para redes inalámbricas definidas por software que se denomina SoftAir. Esto permite manejar tanto un gran número de dispositivos como el volumen de datos que estarán vertiendo en la red. Otra contribución de esta tesis doctoral es la propuesta de una técnica novedosa para el análisis de prestaciones de redes multiservicio de alta capacidad que se basa en un nuevo enfoque del modelizado analítico de sistemas que operan a diferentes escalas temporales. Este enfoque utiliza el análisis del transitorio de una serie de subcadenas absorbentes y lo denominamos absorbing Markov chain approximation (AMCA). Nuestros resultados muestran que para un coste computacional dado, AMCA calcula los parámetros de prestaciones habituales de un sistema con mayor precisión, en comparación con los resultados obtenidos por otr / Nowadays, Internet of Things (IoT) is an essential technology for the upcoming generation of wireless systems. Connectivity is the foundation for IoT, and the type of access required will depend on the nature of the application. One of the leading facilitators of the IoT environment is machine-to-machine (M2M) communication, and particularly, its tremendous potential to offer ubiquitous connectivity among intelligent devices. Cellular networks are the natural choice for emerging IoT and M2M applications. A major challenge in cellular networks is to make the network capable of handling massive access scenarios in which myriad devices deploy M2M communications. On the other hand, cellular systems have seen a tremendous development in recent decades; they incorporate sophisticated technology and algorithms to offer a broad range of services. The modeling and performance analysis of these large multi-service networks is also a challenging task that might require high computational effort. To address the above challenges, we first concentrate on the design and performance evaluation of novel access control schemes to deal with massive M2M communications. Then, we focus on the performance evaluation of large multi-service networks and propose a novel analytical technique that features accuracy and computational efficiency. Our main objective is to provide solutions to ease the congestion in the radio access or core network when massive M2M devices try to connect to the network. We consider the following two types of scenarios: (i) massive M2M devices connect directly to cellular base stations, and (ii) they form clusters and the data is forwarded to gateways that provide them with access to the infrastructure. In the first scenario, as the number of devices added to the network is constantly increasing, the network should handle the considerable increment in access requests. Access class barring (ACB) is proposed by the 3rd Generation Partnership Project (3GPP) as a practical congestion control solution in the radio access and core network. The proper tuning of the ACB parameters according to the traffic intensity is critical, but how to do so dynamically and autonomously is a challenging task that has not been specified. Thus, this dissertation contributes to the performance analysis and optimal design of novel algorithms to implement effectively this barring scheme and overcome the challenges introduced by massive M2M communications. In the second scenario, since the heterogeneity of IoT devices and the hardware-based cellular architectures impose even greater challenges to enable flexible and efficient communication in 5G wireless systems, this dissertation also contributes to the design of software-defined gateways (SD-GWs) in a new architecture proposed for wireless software-defined networks called SoftAir. The deployment of these SD-GWs represents an alternative solution aiming at handling both a vast number of devices and the volume of data they will be pouring into the network. Another contribution of this dissertation is to propose a novel technique for the performance analysis of large multi-service networks. The underlying complexity of the network, particularly concerning its size and the ample range of configuration options, makes the solution of the analytical models computationally costly. However, a typical characteristic of these networks is that they support multiple types of traffic flows operating at different time-scales. This time-scale separation can be exploited to reduce considerably the computational cost associated to determine the key performance indicators. Thus, we propose a novel analytical modeling approach based on the transient regime analysis, that we name absorbing Markov chain approximation (AMCA). For a given computational cost, AMCA finds common performance indicators with greater accuracy, when compared to the results obtained by other approximate methods proposed in the literature. / En l'actualitat, la Internet de les Coses (Internet of Things, IoT) és una tecnologia essencial per a la propera generació de sistemes sense fil. La connectivitat és la base d'IoT, i el tipus d'accés requerit dependrà de la naturalesa de l'aplicació. Un dels principals facilitadors de l'entorn IoT és la comunicació machine-to-machine (M2M) i, en particular, el seu enorme potencial per oferir connectivitat ubiqua entre dispositius intel · ligents. Les xarxes mòbils són l'elecció natural per a les aplicacions emergents de IoT i M2M. Un desafiament important en les xarxes mòbils que actualment está rebent molta atenció és aconseguir que la xarxa siga capaç de gestionar escenaris d'accés massiu en què una gran quantitat de dispositius utilitzen comunicacions M2M. D'altra banda, els sistemes mòbils han experimentat un gran desenvolupament en les últimes dècades: incorporen tecnologia sofisticada i nous algoritmes per oferir una àmplia gamma de serveis. El modelatge i análisi del rendiment d'aquestes xarxes multiservei és també un desafiament important que podria requerir un gran esforç computacional. Per abordar els desafiaments anteriors, en aquesta tesi doctoral ens centrem en primer lloc en el disseny i l'avaluació de les prestacions de nous mecanismes de control d'accés per fer front a les comunicacions massives M2M en xarxes cel · lulars. Posteriorment ens ocupem de l'avaluació de prestacions de xarxes multiservei i proposem una nova tècnica analítica que ofereix precisió i eficiència computacional. El nostre principal objectiu és proporcionar solucions per a alleujar la congestió a la xarxa d'accés ràdio quan un gran nombre de dispositius M2M intenten connectar-se a la xarxa. Considerem els dos tipus d'escenaris següents: (i) els dispositius M2M es connecten directament a les estacions base cel · lulars, i (ii) formen grups i les dades s'envien a concentradors de trànsit (gateways) que els proporcionen accés a la infraestructura. En el primer escenari, atès que el nombre de dispositius afegits a la xarxa augmenta contínuament, aquesta hauria de ser capaç de gestionar el considerable increment en les sol · licituds d'accés. El 3rd Generation Partnership Project (3GPP) ha proposat l'access class barring (ACB) com una solució pràctica per al control de congestió a la xarxa d'accès ràdio i la xarxa troncal. L'ajust correcte dels paràmetres d'ACB d'acord amb la intensitat del trànsit és crític, però com fer-ho de forma dinàmica i autònoma és un problema complex, la solució del qual no està recollida en les especificacions del 3GPP. Aquesta tesi doctoral contribueix a l'anàlisi del rendiment i al disseny de nous algoritmes que implementen efectivament aquest mecanisme, i així superar els desafiaments introduïts per les comunicacions massives M2M en les xarxes mòbils actuals i futures. En el segon escenari, atès que l'heterogeneïtat dels dispositius IoT i les arquitectures cel · lulars basades en hardware imposen desafiaments encara més grans per permetre una comunicació flexible i eficient en els sistemes sense fil 5G, aquesta tesi doctoral també contribueix al disseny de software-defined gateways (SD-GWS) en una nova arquitectura proposada per a xarxes sense fils definides per programari que s'anomena SoftAir. Això permet gestionar tant un gran nombre de dispositius com el volum de dades que estaran abocant a la xarxa. Una altra contribució d'aquesta tesi doctoral és la proposta d'una tècnica innovadora per a l'anàlisi de prestacions de xarxes multiservei d'alta capacitat que es basa en un nou enfocament del modelitzat analític de sistemes que operen a diferents escales temporals. Aquest enfocament utilitza l'anàlisi del transitori d'una sèrie de subcadenes absorbents i l'anomenem absorbing Markov chain Approximation (AMCA). Els nostres resultats mostren que per a un cost computacional donat, AMCA calcula els paràmetres de prestacions habituals d / Tello Oquendo, LP. (2018). Design and Performance Analysis of Access Control Mechanisms for Massive Machine-to-Machine Communications in Wireless Cellular Networks [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/107946

Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs will become necessary to enable ultra-definition resolution high-frequency large-area displays. Amorphous zinc tin oxide (ZTO) TFTs were fabricated by RF magnetron sputter deposition. In this study, the effect of both deposition and post annealing conditions have been evaluated in regards to film structure, composition, surface contamination, and device performance. Both the variation of oxygen partial pressure during deposition and the temperature of the post-deposition annealing were found to have a significant impact on TFT properties. X-ray diffraction data indicated that the ZTO films remain amorphous even after annealing to 600° C. Rutherford backscattering spectrometry indicated that the Zn:Sn ratio of the films was ~1.7:1 which is slightly tin rich compared to the sputter target composition. X-ray photoelectron spectroscopy data indicated that the films had significant surface contamination and that the Zn:Sn ratios changed depending on sample annealing conditions. Electrical characterization of ZTO films using TFT test structures indicated that mobilities as high as 17 cm² V⁻¹ s⁻¹ could be obtained for depletion mode devices. It was determined that the electrical properties of ZTO films can be precisely controlled by varying the deposition conditions and annealing temperature. It was found that the ZTO electrical properties could be controlled where insulating, semiconducting and conducting films could be prepared. This precise control of electrical properties allowed us to incorporate sputter deposited ZTO films into resistive random access memory (RRAM) devices. RRAM are two terminal nonvolatile data memory devices that are very promising for the replacement of silicon-based Flash. These devices exhibited resistive switching between high-resistance states to low-resistance states and low-resistance states to high-resistance states depending on polarity of applied voltages and current compliance settings. The device switching was fundamentally related to the defect states and material properties of metal and insulator layers, and their interfaces in the metalinsulator-metal (MIM) structure. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Jan. 6, 2012 - Jan. 6, 2013

De plus en plus d'applications spécifiques embarquées exigent de larges blocs de mémoires statiques SRAM. En particulier il y a un besoin de mémoires inconditionnellement actives pour lesquelles la consommation d'énergie est un paramètre clé. Par exemple les réseaux sans fil hétérogènes sont caractérisés par plusieurs interfaces tournées vers des réseaux différents, donc de multiples adresses IP simultanées. Une grande quantité de mémoire est mobilisée et pose un sérieux problème de consommation d'énergie vis-à-vis de l'autonomie de système mobile. La stratégie classique d'extinction des blocs mémoire momentanément non opérationnelle ne permet qu'une réduction faible en consommation et limite les performances dynamiques du système. Il y a donc un réel besoin pour une mémoire toujours opérationnelle avec un très faible bilan énergétique. Par ailleurs les technologies CMOS avancées posent le problème de la variabilité et la conception de mémoire SRAM doit aboutir à un niveau de fiabilité très grand. La thèse discute les verrous techniques et industriels concernant la mémoire embarquée SRAM très faible consommation. Le cas de la mémoire toujours opérationnelle représente un défi pertinent. Un état de l'art balaie les architectures SRAM avec plusieurs points de vue. Une discussion à propos de la modélisation analytique statistique comme moyen de simplification de la conception en 32nm a été développée. Une cellule alternative aux 6T, 7T et 8T, laquelle est appelée 5T-Portless présente des avantages et des performances qui repose sur son fonctionnement en mode courant à l'origine de la réduction significative de la consommation dynamique ajoutée à une cellule intrinsèquement peu fruiteuse. Un démonstrateur de 64kb (1024x64b) en CMOS32nm a été réalisé, les résultats de mesure confirment l'intérêt industriel de cette mémoire. / The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.

Cette étude porte sur des oxydes TiO2, SrTiO3 et SrZrO3 déficients en oxygène ou dopés par des ions de métaux de transition. Nous avons préparé des échantillons sous forme de polycristaux, de monocristaux et de films minces. Leurs propriétés structurelles, physiques et électroniques ont été mesurées à l’aide de techniques sensibles aux volumes (diffraction des rayons X, magnétométrie SQUID, résonance paramagnétique électronique) ou sensibles aux surfaces (spectroscopie de photoémission, spectroscopie d’absorption X). Les mesures de RPE et au SQUID permettent non seulement d’obtenir leurs propriétés magnétiques mais également la valence des ions Cr dopant. Nous avons ainsi pu établir les paramètres clés qui contrôlent la valence des ions chrome lors de la synthèse. Des phases secondaires telles que SrCrO4 peuvent se former quand les échantillons sont synthétisés dans des atmosphères riches en oxygène. Les propriétés de films SrZrO3 dopés au chrome sont également discutées. Leurs conditions de préparation influencent non seulement le comportement des ions chrome mais également celui de la commutation de résistivité. Ce dernier semble dépendre de la chimie de surface des films. L’accumulation d’ions Cr3+ au voisinage de la surface fournit une interface propre exempte d’oxydes non stœchiométriques. Cette terminaison nette de l’interface a pour résultat de bonnes performances de la commutation de résistivité. / In this study, the oxygen-deficient TiO2, SrTiO3 systems and transition metal ion (Cr or V) doped TiO2, SrTiO3 and SrZrO3 systems have been investigated. We prepared samples as polycrystals, single crystals and thin films for various desires. Their structural, physical and electronic properties were measured by bulk-sensitive techniques (X-Ray Diffraction, SQUID and Electro Paramagnetic Resonance) or surface-sensitive techniques (Photoemission spectroscopy and X-ray absorption spectroscopy). The measurement of SQUID and EPR showed not only their magnetic properties but also the valence state of Cr dopant. We verified the valence state of Cr ions in oxides and found the key parameters of sample synthesis which control the valence state of Cr ions. Segregated phases such as SrCrO4 were formed when the samples were synthesized under O2 rich environment. The surface properties of Cr doped SrZrO3 films are also discussed. We found the synthesis conditions which influence on not only the behavior of Cr ions but also the resistive-switching behaviors. Various resistive-switching behaviors seem to depend on the surface chemistry of films. We found that the accumulation of Cr3+ on film surface provides a clean interface without any non-stoichiometric oxides and that this sharp interface termination results in a good performance of resistive-switching.

Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques. / text

Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the transistor count is as large as billions of gate for some of the microprocessors. The design complexity is further projected to increase in the coming years in accordance with Moore's law. The larger gate count and integration of multiple functionalities are the causes for higher test power dissipation, test time and data volume. The dynamic power dissipation during scan testing, i.e. during scan shift, launch and response capture, are major concerns for reliable as well as cost effective testing. Excessive average power dissipation leads to a thermal problem which causes burn-out of the chip during testing. Peak power on other hand causes test failure due to power induced additional delay. The test failure has direct impact on yield. The test power problem in modern 3D stacked based IC is even a more serious issue. Estimating the worst case functional power dissipation is yet another great challenge. The worst case functional power estimation is necessary because it gives an upper bound on the functional power dissipation which can further be used to determine the safe power zone for the test. Several solutions in the past have been proposed to address these issues. In this thesis we have three major contributions: 1) Sequential scan chain reordering, and 2) JScan-an alternative Joint-scan DFT architecture to address primarily the test power issues along with test time and data volume, and 3) an integer linear programming methodology to address the power estimation problem. In order to reduce test power during shift, we have proposed a graph theoretic formulation for scan chain reordering and for optimum scan shift operation. For each formulation a set of algorithms is proposed. The experimental results on ISCAS-89 benchmark circuit show a reduction of around 25% and 15% in peak power and scan shift time respectively. In order to have a holistic DFT architecture which could solve test power, test time, and data volume problems, a new DFT architecture called Joint-scan (JScan) have been developed. In JScan we have integrated the serial and random access scan architectures in a systematic way by which the JScan could harness the respective advantages from each of the architectures. The serial scan architecture from test power, test time, and data volume problems. However, the serial scan is simple in terms of its functionality and is cost effective in terms of DFT circuitry. Whereas, the random ac-cess scan architecture is opposite to this; it is power efficient and it takes lesser time and data volume compared to serial scan. However, the random access scan occupies larger DFT area and introduces routing congestion. Therefore, we have proposed a methodology to realize the JScan architecture as an efficient alternative for standard serial and random access scan. Further, the JScan architecture is optimized and it resulted into a 2-Mode 2M-Jscan Joint-scan architecture. The proposed architectures are experimentally verified on larger benchmark circuits and compared with existing state of the art DFT architectures. The results show a reduction of 50% to 80% in test power and 30% to 50% in test time and data volume. The proposed architectures are also evaluated for routing area minimization and we obtained a saving of around 7% to 15% of chip area. Estimating the worst case functional power being a challenging problem, we have proposed a binary integer linear programming (BILP) based methodology. Two different formulations have been proposed considering the different delay models namely zero-delay and unit-delay. The proposed methodology generates a pair or input vectors which could toggle the circuit to dissipate worst power. The BILP problems are solved using CPLEX solver for ISCAS-85 combinational benchmark circuits. For some of the circuits, the proposed methodology provided the worst possible power dissipation i.e. 80 to 100% toggling in nets.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.