Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA. / Ph. D.

Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-length programmable interconnects are slow. It is expected that this architectural enhancement, based on wire emulation techniques, can reduce chip-length communication latency and routing congestion. A prototype wire emulation system that uses FPGA self-reconfiguration as a non-traditional means of intra-FPGA communication is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis. / Master of Science

Adaptive computing systems have proven useful for implementing a wide range of algorithms. A limitation of current systems is the relatively small amount of reconfigurable hardware resources. Many algorithms require more hardware resources than are available. One solution to this problem is runtime reconfiguration (RTR). Using RTR techniques, a large algorithm is implemented as a collection of configurations for the reconfigurable hardware. These configurations are loaded onto the reconfigurable hardware as necessary to implement the algorithm. A primary limitation of RTR is that the reconfiguration process is slow. Therefore, methods of decreasing reconfiguration time are desirable. Another method of implementing large algorithms on small hardware is to use multiple configurable computing platforms connected via a communication network. RTR techniques can be used in conjunction with this method to further increase hardware availability. In this case reconfiguration time is increased by the overhead of transmitting data across the communication network. Methods of decreasing network overhead are desirable. This thesis discusses the use of caching techniques to decrease reconfiguration time. An architecture for caching configurations is implemented on a configurable computing system platform. The use of caching to decrease network overhead is discussed and exhibited. An example application is implemented and used to evaluate the effects of caching on reconfiguration time and algorithm performance. / Master of Science

The reprogrammable nature of configurable computing machines has led to a wealth of research in run-time reconfigurable systems and applications. A limitation often encountered in this research is the slow configuration time with respect to the system clock speed. One technique to deal with these configuration delays has been to develop devices that can hold multiple rapidly interchangeable configurations. This technique is known as context-switching. This thesis discusses the development of a framework to support applications which execute on a run-time reconfigurable system containing context-switching devices. The framework is divided into a number of layers: hardware, middleware, software, and applications. The design, implementation, and details of each layer are presented. / Master of Science

A distinctive feature of run-time reconfigurable systems is the ability to change the configuration of programmable resources during execution. This opens a number of possibilities such as virtualisation of computational resources, simplified routing and in certain applications lower power. Seamless run-time reconfiguration requires rapid configuration. Commodity programmable devices have relatively long configuration time, which makes them poor candidates for run-time reconfigurable systems. Reducing this reconfiguration time to the order of nano seconds will enable rapid run-time reconfiguration. Having multiple configuration planes and switching between them while processing data is one approach towards achieving rapid reconfiguration. An experimental context switching programmable device, called the Context Switching Reconfigurable Computer (CSRC), has been created by BAE Systems, which provided opportunities to explore context-switching strategies for run-time reconfigurable systems. The work presented here studies this approach for run-time reconfiguration, by applying the concepts to develop applications on a context switching reconfigurable system. The work also discusses the advantages and disadvantages of such an approach and ways of leveraging the concept for efficient computing. / Master of Science

Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.

Le sujet de cette thèse s'inscrit dans le cadre des systèmes tolérants aux défauts sous contraintes avec prise en considération de la dégradation des performances. L'objectif principal de ce travail consiste à considérer la gestion des références comme une partie intégrante du système de commande tolérant aux défauts. Dans la littérature, la plupart des méthodes actives de tolérance aux défauts supposent que le recouvrement du système nominal est toujours possible et que les performances nominales sont toujours atteignables. Cette condition est peu réaliste dans la pratique puisque plusieurs éléments empêchent le système reconfiguré de revenir à son mode de fonctionnement nominal. Dans le domaine industriel, l'ensemble des contraintes du système est un handicap majeur qui limite le fonctionnement nominal d'un système à des plages fonctionnelles bien définies. Ces plages fonctionnelles sont énormément réduites après l'apparition de certains défauts dits sévères et qui affectent généralement les actionneurs. Par conséquent, cette hypothèse de recouvrement des performances nominales dans le cas des systèmes sous contraintes limite l'ensemble des défauts traités par ces méthodes classiques à quelques défauts dits mineurs. Afin de remédier a ce problème, une architecture de reconfiguration structurée en deux niveaux est proposée. Le premier concerne les algorithmes classiques de reconfiguration en agissant sur un contrôleur reconfigurable, et le deuxième agit sur le module de gestion des références conçu à base d'un gouverneur de référence avec offset. La connaissance exacte du modèle en post-défaut nécessite un système de détection et diagnostic de défaut qui permet d'estimer l'amplitude de défaut, ce qui conduit à la synthèse d'un observateur adaptatif d'estimation de défaut à base de LMI. Afin de synchroniser le déroulement du processus FTC, deux indices ont été conçus. Le premier indice porte sur le mécanisme de décision permettant de sélectionner le/les niveau(x) de reconfiguration nécessaire(s) à l'accommodation du défaut. Le deuxième indice permet d'évaluer le niveau de dégradation du système « post-défaut ». Une dégradation de performance est toujours admise tant que les consignes de sécurité sont respectées / The subject of this thesis is part of fault tolerant control systems under constraints with consideration of performance degradation. The main objective of this work is to consider the reference management as an integral part of the fault tolerant control system. In the literature, the most active methods of fault tolerance imply that recovery of the nominal system is always possible and that performance ratings are still achievable. This requirement is unrealistic in practice because several factors prevent the system reconfigured back to its nominal operating mode. In industry, the set of system constraints is a major problem which limits the nominal operating of the system to defined functional ranges. These functional ranges are reduced dramatically after the occurrence of some faults known as severe faults that generally affect the capacity of actuators. Therefore, this assumption of nominal performance recovery in the case of systems under constraints limits the set of faults treated with these conventional methods to a few minor faults. To remedy this problem, architecture of reconfiguration structured in two levels is proposed. The first level concerns the conventional reconfiguration algorithms acting on a reconfigurable controller, and the second acts on the module of reference management based on a reference-offset governor. The exact knowledge of the post-fault model requires a fault detection and diagnosis system to estimate the magnitude of fault, which led to the synthesis of an adaptive observer based LMI for estimating fault. To synchronize the FTC process flow, two indices have been designed. The first index refers to the decision mechanism for selecting the reconfiguration level required for the accommodation of the fault. The second index used to evaluate the level of the degradation of the system "post-fault". The performance degradation is still allowed as long as safety instructions are respected

Les systèmes adaptatifs basés sur les architectures FPGA (Field-Programmable Gate Arrays) peuvent bénéficier grandement de la grande flexibilité offerte par la reconfiguration partielle dynamique (DPR). Grâce au DPR, les tâches matérielles composant un système adaptatif peuvent être allouées et re-allouées à la demande ou en fonction de l'environnement dynamique. Les flots de conceptions disponibles et les outils commerciaux ont évolué pour répondre aux exigences des architectures reconfigurables qui sont toutefois limitées dans leurs fonctionnalités. Ces outils ne permettent pas un placement et une relocation efficaces de tâches matérielles de tailles variables. L'objectif principal de ces travaux de thèse consiste à proposer des nouvelles méthodologies et de nouvelles approches pour faciliter au concepteur la phase de conception d'un système adaptatif reconfigurable opérationnelle, valide, optimisé et adapté aux changements dynamiques de l'environnement. La première contribution de cette thèse porte sur la problématique de la relocation des tâches matérielles de tailles différentes. Une méthodologie de conception est proposée pour répondre à un problème majeur des mécanismes de relogement : le stockage d'une unique bitstream de configuration pour réduire les besoins de la mémoire et pour accroître la réutilisable des modules matériels générés. Une technique de partitionnement de la région reconfigurable est appliquée dans la méthodologie de relogement proposée pour augmenter l'efficacité d'utilisation des ressources matérielles dans le cas des tâches reconfigurables de tailles variables. Cette méthodologie prend en compte aussi la communication entre différentes régions reconfigurables et la région statique. Pour valider la méthode, plusieurs études de cas sont implémentées. Cette validation montre une utilisation efficace des ressources matérielles ainsi une réduction importante du temps de reconfiguration. La deuxième partie de cette thèse présente et détaille une formulation mathématique afin d'automatiser le floorplanning des zones reconfigurables dans les FPGAs. Les algorithmes de recherche présentés dans cette thèse sont basés sur la technique d'optimisation PLMNE (programmation linéaire mixte en nombres entiers). Ces algorithmes permettent de définir automatiquement l'emplacement, la taille et la forme de la zone reconfigurable dynamique. Nous nous intéressons principalement dans cette recherche à la satisfaction des contraintes de placement des zones reconfigurables et celles liées à la relocation. De plus, nous considérons l’optimisation des ressources matérielles dans le FPGA en tenant compte des tâches de tailles variables. Finalement, une évaluation de l'approche proposée est présentée / Adaptive systems based on Field-Programmable Gate Arrays (FPGA) architectures can benefit greatly from the high degree of flexibility offered by dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. Existing design flows and commercial tools have evolved to meet the requirements of reconfigurables architectures, but that are limited in functionality. These tools do not allow an efficient placement and relocation of variable-sized hardware tasks. The main objective of this thesis is to propose a new methodology and a new approaches to facilitate to the designers the design phase of an adaptive and reconfigurable system and to make it operational, valid, optimized and adapted to dynamic changes in the environment. The first contribution of this thesis deals with the issues of relocation of variable-sized hardware tasks. A design methodology is proposed to address a major problem of relocation mechanisms: storing a single configuration bitstream to reduce memory requirements and increasing the reusability of generating hardware modules. A reconfigurable region partitioning technique is applied in this proposed relocation methodology to increase the efficiency of use of hardware resources in the case of reconfigurable tasks of variable sizes. This methodology also takes into account communication between different reconfigurable regions and the static region. To validate the design method, several cases studies are implemented. This validation shows an efficient use of hardware resources and a significant reduction in reconfiguration time. The second part of this thesis presents and details a mathematical formulations in order to automate the floorplanning of the reconfigurable regions in the FPGAs. The algorithms presented in this thesis are based on the optimization technique MILP (mixed integer linear programming). These algorithms allow to define automatically the location, the size and the shape of the dynamic reconfigurable region. We are mainly interested in this research to satisfy the constraints of placement of the reconfigurable zones and those related to the relocation. In addition, we consider the optimization of the hardware resources in the FPGA taking into account the tasks of variable sizes. Finally, an evaluation of the proposed approach is presented

Les réserves limitées de combustibles fossiles et la pollution entrainée par les gaz produits ouvrent la voie à desressources énergétiques renouvelables (RER) alternatives et prometteuses telles que les ressources solaires (RS)et les ressources éoliennes (RE). Ces ressources sont librement disponibles et respectueuses de l'environnement.Cependant, les RER sont de nature intermittente. Par conséquent, il existe un besoin de lissage des fluctuations depuissance en stockant l'énergie pendant les périodes de surproduction pour la restituer au réseau lorsque lademande énergétique devient importante. Les systèmes de stockage de l'énergie (SSE) peuvent alors être utilisésde manière appropriée à cette fin.L'utilisation de plusieurs sources d'énergie et de stockeurs pour construire des systèmes de puissance hybrides(SPH) exige une stratégie de gestion de l'énergie pour atteindre le minimum de coût des SPH et un équilibre entrela production et la consommation de l'énergie. Cette méthode de gestion de l'énergie est un mécanisme pourobtenir une production d'énergie idéale et pour satisfaire convenablement la demande de charge à rendementrelativement élevé.Dans cette thèse, un SPH intégrant production électrique photovoltaïque, éolienne, une micro-turbine à gaz ainsiqu'un système de stockage de l'électricité par le vecteur hydrogène est considéré. Le but de cette hybridation estde construire un système fiable, qui est en mesure de fournir la charge et qui a la capacité de stocker l'énergieexcédentaire sous forme hydrogène et de la réutiliser plus tard. En outre, le problème d'ombrage partiel dePanneaux Photovoltaïques est étudié de manière approfondie. Une nouvelle solution basée sur des interrupteurssimples et un contrôle par logique floue intégré dans une carte électronique dSPACE a été proposée. Unereconfiguration des panneaux photovoltaïques en temps réel et de déconnexion de ceux ombragés est égalementeffectuée en cherchant à minimiser les pertes de puissance. Le couplage thermique entre ces panneauxphotovoltaïques et un électrolyseur à membrane polymère est également étudié, à l'échelle système. Enrécupérant une partie de l'énergie thermique reçue par les panneaux, une amélioration du rendement du systèmehybride PPVELS MEP est réalisée / The limited reserves of fossil fuel and the pollution gases produced pave the way to promising alternativeRenewable Energy Sources (RESs) such as Solar Energy Sources (SESs) and Wind Energy Sources (WESs).SESs and WESs are freely available and environmentally friendly. However, RESs are intermittent in nature.Therefore, the smoothing of power fluctuations by storing the energy during periods of oversupply and restore it tothe grid when demand becomes necessary. Accordingly, Energy Storage Systems (ESSs) can be appropriatelyused for this purpose.Using several energy sources for constructing HPSs alongside with ESS will require an energy managementstrategy to achieve minimum HPS cost and optimal balance between energy generation and energy consumption.This energy management method is a mechanism to achieve an ideal energy production and to conveniently satisfythe load demand at relatively high efficiency.In this thesis, a Hybrid Power System (HPS) including Renewable Energy Sources (RESs) such as main sourcescombined with Gas Micro-Turbine (GMT) and hydrogen storage system such as Back-up Sources (BKUSs) hasbeen presented. The aim of this hybridization is to build a reliable system, which is able to supply the load andhaving the ability to store the excess energy in hydrogen form and reuse it later when demanded. Consequently, thestored energy at the end of each cycle will be zero and a minimum generated power cost is achieved. In addition,partial shading problem of Photovoltaic (PV) panels is comprehensively studied and a new solution based on simpleswitches and Fuzzy Logic Control (FLC) integrated into dSPACE electronic card is created. Consequently, a realtime PV panels reconfiguration and disconnecting shaded ones is performed and minimum power losses isachieved. Then, the PV panels are connected to a Proton Exchange Membrane Electrolyser (PEM ELS). Theemitted temperature by the PV panels is transferred to the endothermic element PEM ELS. Consequently, anefficiency enhancement of the hybrid system PVPEM ELS is realized.

Communication and reconnaissance systems are requiring increasing flexibility concerning functionality and efficiency for multiband and broadband frequency applications. Circuit-based reconfiguration mechanisms continue to promote radio frequency (RF) application flexibility; however, increasing limitations have resulted in hindering performance. Therefore, the implementation of a "wireless" reconfiguration mechanism provides the required agility and amicability for microwave circuits and antennas without local overhead. The wireless reconfiguration mechanism in this thesis integrates dynamic, fluidic-based material systems to achieve electromagnetic agility and reduce the need for "wired" reconfiguration technologies. The dynamic material system component has become known as electromagnetically functionalized colloidal dispersions (EFCDs). In a microfluidic reconfiguration system, they provide electromagnetic agility by altering the colloidal volume fraction of EFCDs - their name highlights the special considerations we give to material systems in applied electromagnetics towards lowering loss and reducing system complexity. Utilizing EFCDs at the RF device-level produced the first circuit-type integration of this reconfiguration system; this is identified as the coaxial stub microfluidic impedance transformer (COSMIX). The COSMIX is a small hollowed segment of transmission line with results showing a full reactive loop (capacitive to inductive tuning) around the Smith chart over a 1.2 GHz bandwidth. A second microfluidic application demonstrates a novel antenna reconfiguration mechanism for a 3 GHz microstrip patch antenna. Results showed a 300 MHz downward frequency shift by dielectric colloidal dispersions. Magnetic material produced a 40 MHz frequency shift. The final application demonstrates the dynamically altering microfluidic system for a 3 GHz 1x2 array of linearly polarized microstrip patch antennas. The parallel microfluidic capillaries were imbedded in polydimethylsiloxane (PDMS). Both E- and H-plane designs showed a 250 MHz frequency shift by dielectric colloidal dispersions. Results showed a strong correlation between decreasing electrical length of the elements and an increase of the volume fraction, causing frequency to decrease and mutual coupling to increase. Measured, modeled, and analytical results for impedance, voltage standing wave ratio (VSWR), and radiation behavior (where applicable) are provided.