Les architectures logicielles ont un rôle important dans le développement de systèmes à logiciel prépondérant afin de permettre la satisfaction tant des exigences fonctionnelles que des exigences extra-fonctionnelles. En particulier, les architectures logicielles dynamiques ont émergé pour faire face aux caractéristiques des systèmes contemporains qui opèrent dans des environnements dynamiques et par conséquent susceptibles de changer en temps d’exécution. Les langages de description architecturale (ADLs) sont utilisés pour représenter les architectures logicielles en produisant des modèles qui peuvent être utilisés pendant la conception ainsi que l’exécution. Cependant, la plupart des ADLs existants sont limités sur plusieurs facettes : (i) ils ne décrivent que les aspects structurels, topologiques de l’architecture ; (ii) ils ne fournissent pas un support adéquat pour représenter les aspects comportementaux de l’architecture ; (iii) ils ne permettent pas de décrire des aspects avancés de la dynamique de l’architecture ; (iv) ils sont limités en ce qui concerne la vérification automatisée des propriétés et des contraintes architecturales ; et (v) ils sont déconnectés du niveau d’implémentation et entraînent souvent des incohérences entre l’architecture et l’implémentation. Pour faire face à ces problèmes, cette thèse propose un framework formel pour les architectures logicielles dynamiques. Ce framework comprend : (i) .-ADL, un langage formel pour décrire des architectures logicielles dynamiques sous les perspectives structurelles et comportementales ; (ii) la spécification des opérations de reconfiguration dynamique programmée ; (iii) la génération automatique de code source à partir des descriptions architecturales ; et (iv) une approche basée sur la vérification statistique pour exprimer et vérifier formellement des propriétés des architectures logicielles dynamiques. Les contributions principales apportées par le framework proposé sont quatre. Premièrement, le langage .-ADL a été doté de primitives de niveau architectural pour décrire des reconfigurations dynamiques programmées. Deuxièmement, les descriptions architecturales dans .-ADL sont transformées vers le code source d’implémentation dans le langage de programmation Go, en contribuant à minimiser les dérives architecturales. Troisièmement, une nouvelle logique appelée DynBLTL est utilisée pour exprimer formellement des propriétés dans les architectures logicielles dynamiques. Quatrièmement, un outil basé sur SMC a été développé pour automatiser la vérification des propriétés architecturales en cherchant à réduire l’effort, les ressources computationnelles, et le temps pour réaliser cette tâche. Dans ce travail, deux systèmes basés sur réseaux de capteurs sans fil sont utilisés pour valider les éléments du framework. / Software architectures play a significant role in the development of software-intensive systems in order to allow satisfying both functional and non-functional requirements. In particular, dynamic software architectures have emerged to address characteristics of the contemporary systems that operate on dynamic environments and consequently subjected to changes at runtime. Architecture description languages (ADLs) are used to represent software architectures, producing models that can be used at design time and/or runtime. However, most existing ADLs have limitations in several facets: (i) they are focused on structural, topological aspects of the architecture; (ii) they do not provide an adequate support for representing behavioral aspects of the architecture; (iii) they do not allow describing advanced aspects regarding the dynamics of the architecture; (iv) they are limited with respect to the automated verification of architectural properties and constraints; and (v) they are disconnected from the implementation level, thus entailing inconsistencies between architecture and implementation. In order to tackle these problems, this thesis proposes formally founded framework for dynamic software architectures. Such a framework comprises: (i) .-ADL, a formal language for describing software architectures under both structural and behavioral viewpoints; (ii) the specification of programmed dynamic reconfiguration operations; (iii) the automated generation of source code from architecture descriptions; and (iv) an approach based on statistical model checking (SMC) to formally express and verify properties in dynamic software architectures. The main contributions brought by the proposed framework are fourfold. First, the .-ADL language was endowed with architectural-level primitives for describing programmed dynamic reconfigurations. Second, architecture descriptions in .-ADL are translated towards implementation source code in the Go programming language, thereby contributing to minimize architectural drifts. Third, a novel logic, called DynBLTL, is used to formally express properties in dynamic software architectures. Fourth, a toolchain relying on SMC was built to automate the verification of architectural properties while striving to reduce effort, computational resources, and time for performing such a task. In this work, two wireless sensor network-based systems are used to validate the framework elements.

Spacecraft formation flying refers to the coordinated operation of a group of spacecraft with a common objective. While the concept has been in existence for a long time, practical fruition of the ideas was not possible earlier due to technological limitations. The topic has received widespread attention in the last decade, with the development of autonomous control, improved computational facilities and better communication technology. It allows a number of small, lightweight, economical spacecraft to work together to execute the function of a larger, heavier, more complex and expensive spacecraft. The primary advantage of such systems is that they are flexible, modular, and cost-effective.<div><br></div><div>The flexibility of formation flying and other derived concepts comes from the fact that the units are not physically attached, allowing them to change position or orientation when the need arises. To fully realize this possibility, it is important to develop methods for spatial reorganization. This thesis is an attempt to contribute to this development. </div><div><br></div><div>In this thesis, the reconfiguration problem has been formulated as a single system with multiple inputs and multiple outputs, while preserving the individuality of the agents to a certain degree. The agents are able to communicate with their neighbors by sharing information. In this framework, a distributed closed-loop stabilizing controller has been developed, that would drive the spacecraft formation to a target shape. An expression for the controller gain as a function of the graph Laplacian eigenvalues has also been derived. The practical applications of this work have been demonstrated through simulations</div>

With the More Electric Aircraft paradigm, commercial commuter aircraft are increasing the size and complexity of electrical power systems by increasing the number of electrical loads. With this increase in complexity comes a need to analyze electrical power systems using new tools. The Hybrid Power System Optimizer (HyPSO) developed by Airbus SAS is a simulator designed to analyze new aircraft power systems. This thesis project will first provide a method to assess the reliability of complex aircraft electrical power systems before and after failure and reconfiguration events. Next, an add-on to HyPSO is developed to integrate the previously developed reliability calculations. Proof-of-concepts including new data visualizations are performed and provided.

The purpose of this master thesis is to contribute a service-based decentralized architecture for Electronic Control Unit (ECU) with fault tolerant control. As ECU systems are becoming large-scaled, centralized-architecture fault tolerant control is facing challenges in performance, complexity and engineering, for its dependencies, non-modular, non-scalable and so on. In Scania’s ECUs, the architecture is applied by a centralized diagnose system. In this thesis, an alternative solution – service-based decentralized architecture is presented. In the architecture, both diagnostic and reconfiguration are completely decentralized in modules of ECU system. Modules can be seen as a software component with self fault tolerant control abilities, which provides different quality of service to system. A purely service view of ECU system can be built as the foundation both for fault tolerant control architecture and for modeling control system. The thesis project is, firstly to implement a general decentralized diagnostic platform which can be called by modules of Scania Exhaust Emission Control system (EEC3) system. A centralized communication node is constructed for off-board diagnosis by PC-tools. Lastly, service based architecture is built in EEC3 PUMC module as service provider.

The increase of electronics in road vehicles comes along with a broad variety of possibilitiesin terms of safety, handling and comfort for the users. A rising complexityof the vehicle subsystems and components accompanies this development and has tobe managed by increased electronic control. More potential elements, such as sensors,actuators or software codes, can cause a failure independently or by mutually influencingeach other. There is a need of a structured approach to sort the faults from avehicle dynamics stability perspective.This thesis tries to solve this issue by suggesting a fault classification method and faulttolerantcontrol strategies. Focus is on typical faults of the electric driveline and thecontrol system, however mechanical and hydraulic faults are also considered. Duringthe work, a broad failure mode and effect analysis has been performed and the faultshave been modeled and grouped based on the effect on the vehicle dynamic behaviour.A method is proposed and evaluated, where faults are categorized into different levelsof controllability, i. e. levels on how easy or difficult it is to control a fault for the driver,but also for a control system.Further, fault-tolerant control strategies are suggested that can handle a fault with acritical controllability level. Two strategies are proposed and evaluated based on thecontrol allocation method and an electric vehicle with typical faults. It is shown thatthe control allocation approaches give less critical trajectory deviation compared to noactive control and a regular Electronic Stability Control algorithm.To conclude, this thesis work contributes with a methodology to analyse and developfault-tolerant solutions for electric vehicles with improved traffic safety. / <p>QC 20131010</p>

For applications such as live video processing, there is a high demand for high performance and low latency solutions. The configurable logic in FPGAs allows for custom hardware to be tailored to a specific video application. These FPGA designs require technical expertise and lengthy implementation times by vendor tools for each unique solution. This thesis presents a dynamically configurable topology as an FPGA overlay to deploy custom hardware processing pipelines during run-time by utilizing dynamic partial reconfiguration. Within the FPGA overlay, a configurable topology with a routable switch allows video streams to be copied and mixed to create complex data paths. This work demonstrates a dynamic video processing pipeline with 11 reconfigurable regions and 16 unique processing cores, allowing for billions of custom run-time configurations.

Les systèmes de communication ont besoin d'accéder, stocker, manipuler, ou de communiquer des informations sensibles. Par conséquent, les primitives cryptographiques tels que les fonctions de hachage et le chiffrement par blocs sont déployés pour fournir le cryptage et l'authentification. Récemment, des techniques ont été inventés pour combiner cryptage et d'authentification en un seul algorithme qui est appelé authentifiés Encryption (AE). La combinaison de ces deux services de sécurité dans le matériel de meilleures performances par rapport aux deux algorithmes séparés puisque l'authentification et le cryptage peuvent partager une partie du calcul. En raison de la combinaison de la programmation de l'exécution d'matériel personnalisé, FPGA deviennent plus communs comme cible d'une mise en œuvre de ces algorithmes. La première partie de cette thèse est consacrée aux architectures d'algorithmes AE, AES-GCM et AEGIS-128 à base de FPGA efficaces et à grande vitesse, afin d'être utilisé dans la partie reconfigurable FPGA pour soutenir les services de sécurité des systèmes de communication. Notre focalisation sur l'état de l'art conduit à la mise en place d'architectures à haute vitesse pour les applications lentes touches changeantes comme les réseaux privés virtuels (VPN). En outre, nous présentons un procédé efficace pour mettre en oeuvre le GF($2^{128}$) multiplicateur, qui est responsable de la tâche d'authentification en AES-GCM, pour supporter les applications à grande vitesse. En outre, un système efficace AEGIS-128 est également mis en œuvre en utilisant seulement cinq tours AES. Nos réalisations matérielles ont été évaluées à l'aide Virtex-5 et Virtex-4 FPGA. La performance des architectures présentées (Thr. / Parts) surpasse ceux signalés précédemment.La deuxième partie de la thèse présente des techniques pour des solutions à faible coût afin de garantir la reconfiguration du FPGA. Nous présentons différentes gammes de mises en œuvre à faible coût de AES-GCM, AES-CCM, et AEGIS-128, qui sont utilisés dans la partie statique du FPGA afin de décrypter et authentifier le bitstream FPGA. Architectures ASIC présentées ont été évaluées à l'aide de 90 et 65 technologies nm et présentent de meilleures performances par rapport aux travaux antérieurs. / Communication systems need to access, store, manipulate, or communicate sensitive information. Therefore, cryptographic primitives such as hash functions and block ciphers are deployed to provide encryption and authentication. Recently, techniques have been invented to combine encryption and authentication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces better performance compared to two separated algorithms since authentication and encryption can share a part of the computation. Because of combining the programmability with the performance ofcustom hardware, FPGAs become more common as an implementation target for such algorithms. The first part of this thesis is devoted to efficient and high-speed FPGA-based architectures of AE algorithms, AES-GCM and AEGIS-128, in order to be used in the reconfigurable part of FPGAs to support security services of communication systems. Our focus on the state of the art leads to the introduction of high-speed architectures for slow changing keys applications like Virtual Private Networks (VPNs). Furthermore, we present an efficient method for implementing the GF($2^{128}$) multiplier, which is responsible for the authentication task in AES-GCM, to support high-speed applications. Additionally, an efficient AEGIS-128is also implemented using only five AES rounds. Our hardware implementations were evaluated using Virtex-5 and Virtex-4 FPGAs. The performance of the presented architectures (Thr./Slices) outperforms the previously reported ones.The second part of the thesis presents techniques for low cost solutions in order to secure the reconfiguration of FPGAs. We present different ranges of low cost implementations of AES-GCM, AES-CCM, and AEGIS-128, which are used in the static part of the FPGA in order to decrypt and authenticate the FPGA bitstream. Presented ASIC architectures were evaluated using 90 and 65 nm technologies and they present better performance compared to the previous work.

This dissertation work concentrates on novel reconfiguration technologies, including design, microfabrication, and characterization aspects with an emphasis on their applications to multifunctional recon-figurable antennas. In the literature, reconfigurable antennas have made use of various reconfiguration techniques. The most common techniques utilized revolved around switching mechanisms. Other techniques such as the incorporation of variable capacitors, varactors, and physical structure manipulation surfaced recently to overcome many problems faced in using switches and their biasing. Usage of fluids (micro-fluidic or otherwise) in antennas provides a conceptually easy reconfiguration mechanism in the aspect of physical alteration. However, a requirement of pumps, valves, etc. for liquid transportation makes the antenna implementations rather impractical for the real-life scenarios. This work reports on design and experiments conducted to evaluate the electrowetting on dielectric (EWOD) driven digital microfluidics as a reconguration mechanism for antennas.

The field-programmable gate array (FPGA) is a dynamically reconfigurable digital logic chip used to implement custom hardware. The large densities of modern FPGAs and the capability of the on-thely reconfiguration has made the FPGA a viable alternative to fixed logic hardware chips such as the ASIC. In high-performance computing, FPGAs are used as co-processors to speed up computationally intensive processes or as autonomous systems that realize a complete hardware application. However, due to the limited capacity of FPGA logic resources, denser FPGAs must be purchased if more logic resources are required to realize all the functions of a complex application. Alternatively, partial reconfiguration (PR) can be used to swap, on demand, idle components of the application with active components. This research uses PR to swap components to improve the performance of the application given the limited logic resources available with smaller but economical FPGAs. The swap is called ”resource sharing PR”. In a pipelined design of multiple hardware modules (pipeline stages), resource sharing PR is a technique that uses PR to improve the performance of pipeline bottlenecks. This is done by reconfiguring other pipeline stages, typically those that are idle waiting for data from a bottleneck, into an additional parallel bottleneck module. The target pipeline of this research is a two-stage “slow-toast” pipeline where the flow of data traversing the pipeline transitions from a relatively slow, bottleneck stage to a fast stage. A two stage pipeline that combines FPGA-based hardware implementations of well-known Bioinformatics search algorithms, the X! Tandem algorithm and the Smith-Waterman algorithm, is implemented for this research; the implemented pipeline demonstrates that characteristics of these algorithm. The experimental results show that, in a database of unknown peptide spectra, when matching spectra with 388 peaks or greater, performing resource sharing PR to instantiate a parallel X! Tandem module is worth the cost for PR. In addition, from timings gathered during experiments, a general formula was derived for determining the value of performing PR upon a fast module.

Shipboard Power Systems (SPS) play a significant role in next-generation Navy fleets. With the increasing power demand from propulsion loads, ship service loads, weaponry systems and mission systems, a stable and reliable SPS is critical to support different aspects of ship operation. It also becomes the technology-enabler to improve ship economy, efficiency, reliability, and survivability. Moreover, it is important to improve the reliability and robustness of the SPS while working under different operating conditions to ensure safe and satisfactory operation of the system. This dissertation aims to introduce novel and effective approaches to respond to different types of possible faults in the SPS. According to the type and duration, the possible faults in the Medium Voltage DC (MVDC) SPS have been divided into two main categories: transient and permanent faults. First, in order to manage permanent faults in MVDC SPS, a novel real-time reconfiguration strategy has been proposed. Onboard postault reconfiguration aims to ensure the maximum power/service delivery to the system loads following a fault. This study aims to implement an intelligent real-time reconfiguration algorithm in the RTDS platform through an optimization technique implemented inside the Real-Time Digital Simulator (RTDS). The simulation results demonstrate the effectiveness of the proposed real-time approach to reconfigure the system under different fault situations. Second, a novel approach to mitigate the effect of the unsymmetrical transient AC faults in the MVDC SPS has been proposed. In this dissertation, the application of combined Static Synchronous Compensator (STATCOM)-Super Conducting Fault Current Limiter (SFCL) to improve the stability of the MVDC SPS during transient faults has been investigated. A Fluid Genetic Algorithm (FGA) optimization algorithm is introduced to design the STATCOM's controller. Moreover, a multi-objective optimization problem has been formulated to find the optimal size of SFCL's impedance. In the proposed scheme, STATCOM can assist the SFCL to keep the vital load terminal voltage close to the normal state in an economic sense. The proposed technique provides an acceptable post-disturbance and postault performance to recover the system to its normal situation over the other alternatives.