Esse trabalho é um estudo sobre circuitos resistivos que apresentam a característica da autossimilaridade em sua configuração. A construção desses circuitos é feita de uma maneira recursiva, de forma análoga a um fractal autossimilar. Os circuitos são analisados pelas suas resistências equivalentes, sendo obtida uma condição para convergência desse valor. Os conceitos auxiliares necessários ao tema desta dissertação abordam a representação de um circuito resistivo como um grafo, além de conceitos envolvendo fractais autossimilares. São propostas ao final de cada capítulo atividades interdisciplinares acessíveis a alunos de ensino médio, com conteúdos envolvendo resistência equivalente, sequências, conjuntos, e noções de área e perímetro. / This work is a study of resistive circuits which present a characteristic of self similarity in their configuration. The construction of these circuits is made in a self recursive way, analogously to a self similar fractal. The circuits are analyzed by their equivalent resistance, and a condition for convergence of this quantity is obtained. Auxiliary concepts that are necessary to this dissertation theme treat the resistive circuit as a graph, and concepts involving self similar fractals. It is proposed at the end of each chapter interdisciplinary activities that are accessible to high school students, with topics involving equivalent resistence, sequences, sets, and notions of area and perimeter.

Les mémoires résistives ReRAM (ou memristors) sont destinées à remplacer les mémoires non volatiles Flash. Les ReRAM utilisent le changement de résistance d’une structure MIM (Métal-Isolant-Métal) soumise à un stress en tension. Jusqu’à présent, l’attention était focalisée sur les mécanismes qui régissent la commutation de résistance dans les dispositifs ReRAM. Moins d’attention a été accordée à la variation de capacitance, c'est-à-dire à la variation de capacité des structures MIM lorsque ces dernières sont soumises à un stress en tension. C’est sur ce dernier point que notre travail porte. Nous étudions la variation d’impédance (conductance et capacitance dans le domaine RF) dans des structures MIM à base de HfO2. Au-delà d’une tension seuil (Set) une diminution de la capacitance est observée, conjointement à une augmentation de conductance. Des cycles mémoires capacité-tension (C-V) et conductance-tension (G-V) sont obtenus de manière reproductible. Des caractérisations en fréquence (C-f et G-f), sous différentes polarisations continues, sont effectuées pour mieux comprendre les mécanismes de commutation de l’impédance. La diminution de capacitance dans l’état conducteur (ON) est attribuée au caractère inductif des filaments conducteurs formés pendant l’étape de Set. Les mécanismes de transport conduisant à l’apparition de ce caractère inductif sont discutés. Nous montrons également l’influence du procédé de dépôt (ALD) de HfO2 sur les caractéristiques C-V et G-V, ainsi que les modifications apportées par l’emploi d’une structure bicouche. Ce travail ouvre la voie à la réalisation de dispositifs à mémoire de capacitance (mem-capacitors), et plus généralement de composants à mémoire d’impédance (ZRAM). Le potentiel de ces dispositifs pour réaliser un filtre reconfigurable (programmable en tension) est démontré d’une manière pratique. / Resistive random access memories (ReRAM) hold great potential for replacing Flash memories. A ReRAM memory (or MEMRISTOR) uses a resistive switching phenomenon found in Metal-Insulator-Metal (MIM) structures under a voltage stress. Most researches were focused on the mechanisms governing the resistance switching in ReRAM devices and less attention has been paid to capacitance variation of MIM structures under a voltage stress. Our work is focused on that latter phenomenon. We study impedance variation (conductance and capacitance in the RF domain) in HfO2-based MIM structures. Above a threshold voltage (Set), concurrently to conductance increase, a decrease in the capacitance value is observed. Reproducible capacitance-voltage (C-V) and conductance-voltage (G-V) memory cycles are obtained. Frequency dependent characterizations (C-f and G-f), under different DC bias voltages, are performed with the aim of understanding the mechanisms of impedance switching. The capacitance decrease observed in the conducting (ON) state is attributed to the inductance of the filament created during the Set stage. Transport phenomena responsible for the filament inductive behavior are discussed. Impact of HfO2 deposition process (ALD), as well as the use of bi-layer structures, on C-V and G-V characteristics are shown. This work paves the way for the realization of new capacitance memory devices (mem-capacitors) and most generally for impedance memories (ZRAM). Potential of these devices to design reconfigurable filters (controlled by voltage bias) is demonstrated in a practical way.

Depuis l’apparition du circuit intégré, la performance des dispositifs semi-conducteurs est reliée à leur miniaturisation via le développement de procédés spécifiques tels que la lithographie. Néanmoins, la réduction des dimensions des dispositifs aux échelles nanométriques rend les étapes de patterning de plus en plus complexes et coûteuses (EUV, gestion de plusieurs passes de masque par couche et erreur de placement du/des masque(s) …) et pousse les fabricants de puces à se tourner vers des méthodes alternatives. Dans le but de réduire les coûts de fabrication des circuits intégrés, une approche bottom-up reposant sur l’utilisation de procédés de dépôts sélectifs est désormais envisagée, au détriment des approches conventionnelles top-down basées sur les procédés de lithographie. La solution de dépôt par couche atomique (ALD) est une technique appropriée pour le développement d’un procédé sélectif en raison de sa très grande sensibilité à la chimie de surface. Ce procédé est appelé dépôt sélectif de zone (ASD pour Area Selective Deposition). Il est basé sur un traitement spécifique d'activation ou de désactivation des réactions chimiques de surface avec le précurseur et/ou le réactif en mode ALD. Ces modifications de réactivité peuvent être obtenues en utilisant une couche de germination (activation) ou des groupes organiques tels que des monocouches auto-assemblées (SAM) (désactivation). Une autre voie est de tirer parti du retard inhérent à la croissance (ou temps d’incubation) sur différents substrats. Dans cette thèse, nous avons développé un nouveau procédé ASD d’oxyde métallique en combinant un dépôt de couche atomique et une étape de gravure qui permet de bloquer la croissance sur substrat à base de silicium (Si, SiO2 et SiN) versus un substrat métallique (TiN). L'étape de gravure est réalisée par addition de NF3 dans un plasma d'oxygène tous les n cycles du procédé PEALD. Nous avons utilisé ce procédé pour le dépôt de deux oxydes actuellement à l'étude pour les applications de mémoires résistives non-volatiles : Ta2O5 et TiO2. Le but des dépôts sélectifs pour l'application mémoire est de réaliser des points mémoires localisés métal/isolant/métal en intégration 3D verticale dite VRRAM. / At advanced nodes, lithography starts to dominate the wafer cost (EUV, managing multiple mask passes per layer and pattern placement error….). Therefore, complementary techniques are needed to continue extreme scaling and extend Moore’s law. Selective deposition and etching is one of them because they can be used to increase and enhance patterning capabilities at very low cost. From all the different deposition processes, Atomic Layer Deposition (ALD) is maybe the most suitable technique to develop a selective process due to its very good coverage property and its high surface sensitivity. This process is called Area Selective Deposition and is a selective deposition process for bottom-up construction It is usually based on a specific surface activation or deactivation treatment in order to activate or limit / inhibit chemical reactions with the ALD precursor / reactant. This surface modifications are usually obtained by using seed layer (activation) or organic groups such as Self-Assembled Monolayers (SAM) (deactivation). Another pathway for selective area deposition with ALD is to take advantage of the inherent substrate-dependent growth initiation: this is inherent selectivity based on difference of nucleation delay. In this thesis, we have proposed a new ASD process of thin oxide by combining atomic layer deposition and etching step (super-cycle) for a 3D Vertical RAM integration. This allows the selective growth of a thin oxide on a metal substrate without deposition on an insulator and/or a semi-conductor substrate(s). The etching step is achieved by NF3 addition in an oxygen plasma every n cycles of the PEALD process allowing (1) to etch the oxide layer on Si and/or SiO2 surface while keeping few nanometers of oxide on TiN substrate and (2) to passivate this two surfaces and to add a new incubation time on Si or SiO2 substrates. We used this process for the deposition of two oxides that are currently under study for non-volatile resistive memories applications: Ta2O5 and TiO2. The intention for memory application is to realize a crosspoint memory in Back-End level from a pattern area or a trench area without the photolithography step.

Modern computing workloads such as machine learning and data analytics perform simple computations on large amounts of data. Traditional von Neumann computing systems, which consist of separate processor and memory subsystems, are inefficient in realizing modern computing workloads due to frequent data transfers between these subsystems that incur significant time and energy costs. In-memory computing embeds computational capabilities within the memory subsystem to alleviate the fundamental processor-memory bottleneck, thereby achieving substantial system-level performance and energy benefits. In this dissertation, we explore a new generation of in-memory computing architectures that are enabled by emerging memory technologies and new CMOS-based memory cells. The proposed designs realize Boolean and non-Boolean computations natively within memory arrays.<br><div><br></div><div>For Boolean computing, we leverage the unique characteristics of emerging memories that allow multiple word lines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using single access. We propose Spin-Transfer Torque Compute-in-Memory (STT-CiM), a design for in-memory computing with modifications to peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in-memory computing under process variations utilizing error detecting and correcting codes to control errors during CiM operations. We demonstrate how STT-CiM can be integrated within a general-purpose computing system and propose architectural enhancements to processor instruction sets and on-chip buses for in-memory computing. <br></div><div><br></div><div>For non-Boolean computing, we explore crossbar arrays of resistive memory elements, which are known to compactly and efficiently realize a key primitive operation involved in machine learning algorithms, i.e., vector-matrix multiplication. We highlight a key challenge involved in this approach - the actual function computed by a resistive crossbar can deviate substantially from the desired vector-matrix multiplication operation due to a range of device and circuit level non-idealities. It is essential to evaluate the impact of the errors introduced by these non-idealities at the application level. There has been no study of the impact of non-idealities on the accuracy of large-scale workloads (e.g., Deep Neural Networks [DNNs] with millions of neurons and billions of synaptic connections), in part because existing device and circuit models are too slow to use in application-level evaluation. We propose a Fast Crossbar Model (FCM) to accurately capture the errors arising due to crossbar non-idealities while being four-to-five orders of magnitude faster than circuit simulation. We also develop RxNN, a software framework to evaluate DNN inference on resistive crossbar systems. Using RxNN, we evaluate a suite of large-scale DNNs developed for the ImageNet Challenge (ILSVRC). Our evaluations reveal that the errors due to resistive crossbar non-idealities can degrade the overall accuracy of DNNs considerably, motivating the need for compensation techniques. Subsequently, we propose CxDNN, a hardware-software methodology that enables the realization of large-scale DNNs on crossbar systems with minimal degradation in accuracy by compensating for errors due to non-idealities. CxDNN comprises of (i) an optimized mapping technique to convert floating-point weights and activations to crossbar conductances and input voltages, (ii) a fast re-training method to recover accuracy loss due to this conversion, and (iii) low-overhead compensation hardware to mitigate dynamic and hardware-instance-specific errors. Unlike previous efforts that are limited to small networks and require the training and deployment of hardware-instance-specific models, CxDNN presents a scalable compensation methodology that can address large DNNs (e.g., ResNet-50 on ImageNet), and enables a common model to be trained and deployed on many devices. <br></div><div><br></div><div>For non-Boolean computing, we also propose TiM-DNN, a programmable hardware accelerator that is specifically designed to execute ternary DNNs. TiM-DNN supports various ternary representations including unweighted (-1,0,1), symmetric weighted (-a,0,a), and asymmetric weighted (-a,0,b) ternary systems. TiM-DNN is an in-memory accelerator designed using TiM tiles --- specialized memory arrays that perform massively parallel signed vector-matrix multiplications on ternary values per access. TiM tiles are in turn composed of Ternary Processing Cells (TPCs), new CMOS-based memory cells that function as both ternary storage units and signed scalar multiplication units. We evaluate an implementation of TiM-DNN in 32nm technology using an architectural simulator calibrated with SPICE simulation and RTL synthesis. TiM-DNN achieves a peak performance of 114 TOPs/s, consumes 0.9W power, and occupies 1.96mm2 chip area, representing a 300X improvement in TOPS/W compared to a state-of-the-art NVIDIA Tesla V100 GPU. In comparison to popular quantized DNN accelerators, TiM-DNN achieves 55.2X-240X and 160X-291X improvement in TOPS/W and TOPS/mm2, respectively.<br></div><div><br></div><div>In summary, the dissertation proposes new in-memory computing architectures as well as addresses the need for scalable modeling frameworks and compensation techniques for resistive crossbar based in-memory computing fabrics. Our evaluations show that in-memory computing architectures are promising for realizing modern machine learning and data analytics workloads, and can attain orders-of-magnitude improvement in system-level energy and performance over traditional von Neumann computing systems. <br></div>

With CMOS technology scaling reaching its limitations rigorous research of alternate and competent technologies is paramount to push the boundaries of computing. Spintronic and resistive memories have proven to be effective alternatives in terms of area, power and performance to CMOS because of their non-volatility, ability for logic computing and easy integration with CMOS. However, deeper investigations to understand their physical phenomenon and improve their properties such as writability, stability, reliability, endurance, uniformity with minimal device-device variations is necessary for deployment as memories in commercial applications. Application of these technologies beyond memory and logic are investigated in this thesis i.e. for security of integrated circuits and systems and special purpose memories. We proposed a spintonic based special purpose memory for search applications, present design analysis and techniques to improve the performance for larger word lengths upto 256 bits. Salient characteristics of RRAM is studied and exploited in the design of widely accepted hardware security primitives such as Physically Unclonable Function (PUF) and True Random Number Generators (TRNG). Vulnerability of these circuits to adversary attacks and countermeasures are proposed. Proposed PUF can be implemented within 1T-1R conventional memory architecture which offers area advantages compared to RRAM memory and cross bar array PUFs with huge number of challenge response pairs. Potential application of proposed strong arbiter PUF in the Internet of things is proposed and performance is evaluated theoretically with valid assumptions on the maturity of RRAM technology. Proposed TRNG effectively utilizes the random telegraph noise in RRAM current to generate random bit stream. TRNG is evaluated for sufficient randomness in the random bit stream generated. Vulnerability and countermeasures to adversary attacks are also studied. Finally, in thesis we investigated and extended the application of emerging non-volatile memory technologies for search and security in integrated circuits and systems.

It is known from the literature that conventional voltage and current transformers measure inaccurate values for voltage and current harmonics which are parts of power quality. Maximum bandwidth of conventional current transformers, which are used in electricity transmission and distribution systems, is 1.5-2 kHz and it is lower for conventional voltage transformers. Also, it is known that / voltages in some frequency spectrum are measured higher and voltages in another frequency spectrum are measured lower by the conventional voltage transformers. Furthermore, because of the phase shift of fundamental component caused by the conventional current and voltage transformers, losses and efficiency can not be calculated accurately. In this work, through the simultaneous measurements taken at the same feeder by both conventional transformers and new technology measurement transformers / amplitude and phase shift errors which are caused by conventional transformers depending on frequency and so harmonics, are examined and evaluated. Amplitude coefficients and phase shifts are determined for different types of conventional transformers to be able to calibrate measurement deviation. Through this work, measured data by conventional transformers will be accurate and realistic in terms of harmonic components. This matter is important to determine whether the accurate limits which will be set in the future possibly concerning with harmonics and interharmonics, are surpassed or not / also for punitive sanction.

Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro / m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta / -&Sigma / DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.

Diese Arbeit behandelt mögliche Ursachen der reversiblen Änderung des elektrischen Widerstandes von Praseodym-Kalzium-Manganat (PCMO) durch elektrische Spannungspulse. Für diesen Widerstandsschalteffekt werden entweder chemische oder rein strukturelle Änderungen im PCMO angenommen. In den Experimenten liegt das PCMO als gesputterter Dünnfilm in einem Sandwichkontakt zwischen zwei Edelmetallelektroden vor, wobei die Kontaktflächen durch Strukturierung nur wenige µm² betragen. Um insbesondere die elektrischen Transporteigenschaften der Kontakte und den Einfluss der Grenzflächen zwischen Oxid und Elektroden zu untersuchen, wurden elektrische Charakterisierungen der Sandwichkontakte bei verschiedenen elektrischen Feldstärken, Temperaturen und Magnetfeldern für verschiedene Herstellungsparameter des PCMOs und der Elektroden durchgeführt. Entgegen der üblichen Annahme von Raumladungszonen als bestimmender Faktor des Grenzflächenwiderstandes wurde sowohl in den Grenzflächenwiderständen als auch im Volumenanteil des Films ein elektrischer Transport durch kleine Polaronen beobachtet, wie er von PCMO-Volumenproben bekannt ist. Die damit verbundene Spannungsabhängigkeit der polaronischen Leitfähigkeit, die Änderungen durch elektrisch bzw. magnetisch induzierte kolossale Widerstandseffekte (CER bzw. CMR) sowie negativ-differentielle Effekte in Widerstand bzw. Leitfähigkeit durch Joulesche Erwärmung konnten in den komplexen, stark nicht-linearen Kennlinien zugeordnet werden. Die Befunde legen ein heterogenes Modell für den Grenzflächenwiderstand nahe: Präparationsbedingte, erhöhte Defektdichten, wie z.B. durch Sauerstoffleerstellen, führen lokal zu einem defektinduzierten Metall-Isolator-Übergang und damit zu elektrisch isolierenden Bereichen. Die verbleibenden Bereiche zeigen hingegen noch die Transporteigenschaften von nahezu defektfreien, gut leitfähigem PCMO und bestimmen über ihren effektiven Querschnitt den Grenzflächenwiderstand. Die bei hohen elektrischen Spannungen auftretenden remanenten Schalteffekte konnten einem einzigen Schaltmechanismus mit klar definierter Schaltpolarität zugeordnet werden, obwohl er an beiden Grenzflächen auch gleichzeitig auftreten und sich damit zusammen mit Relaxation- bzw. Akkumulationseffekten in komplexen Widerstandsänderungen überlagern kann. Weder die Wahl der Herstellungsparameter für die PCMO-Schicht noch der Oberelektrode verändern den generellen Schaltmechanismus, wodurch ein struktureller Mechanismus z.B. auf Basis einer empfindlichen langreichweitigen Ladungsordnung im Vergleich zu einer chemischen Änderung sehr unwahrscheinlich wird. Die gemachten Beobachtungen, insbesondere Schaltpolarität und Zeitabhängigkeiten, sind prinzipiell kompatibel mit einer feldgetriebenen Sauerstoff(leerstellen)migration. Hierzu könnte auch die experimentell beobachtete, im Einklang mit Simulationsergebnissen stehende, starke Joulesche Erwärmung während des Schaltens beitragen. Durch eine Änderung der Sauerstoffleerstellenverteilung könnten lokal an den Grenzflächen defektinduzierte Metall-Isolator-Übergänge auftreten, so dass der Widerstandhub als eine Änderung des effektiven Querschnitts der leitfähigen Bereiche an den Grenzflächen zu interpretieren wäre.

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No. of bitstreams: 1 GARCIA_Uanderson_2017.pdf: 25453924 bytes, checksum: 4c34f46362e91f9eb2f88106f805d7f3 (MD5) Previous issue date: 2017-03-14 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / This work covers the investigation and synthesis of nanometric structures of Porous Anodic Alumina PAA, produced from low purity substrates, in aim to obtain selfsustained membranes. The Hard Anodization (HA) and Mild Anodization (MA) processes were used under special conditions through those found in literature. The analyses of results were based in comparing the AAP produced under the same conditions except the applied potential that was different depending on the MA or HA. HA process had its time halved in order to investigate the oxide growth rate and to calibrate the conditions of anodized membrane synthesis over the glass samples. This work also covers the construction of a resistive thermal evaporation PVD system capable of evaporating metals with melting points below 800°C. Through the deposition of successive layers it was possible to obtain metallic films of aluminum with thicknesses above 10 µm, enabling conditions of synthesis of porous anodic alumina on substrates produced by thermal resistive evaporation. The result of membrane synthesis on low purity aluminum substrates was complement to the synthesis of membranes obtained in aluminum evaporated in glass substrates, since the thickness of each deposited film is low if compared to the thickness of the AAP layer. Therefore, it was necessary to make several Al depositions on the same samples, to obtain an aluminum film that was able to support an oxide layer of anodic alumina and with the same characteristics of those obtained by the process of MA. All anodized samples were characterized by scanning electron microscopy, including samples made from metalized aluminum. The micrography obtained from the low purity aluminum membranes were treated by ImageJ software allowing the morphological analysis. AAP membranes obtained from technical Al substrate depicted the formation of branched pore channels, a result of instabilities in applied electric field during Anodization and presence of different alloying elements in the Al substrate. The metalized aluminum film had a larger thickness in the samples positioned in the middle of the sample holder possibly due to different temperature gradients of filament depending on the position of Al pellets. / Este trabalho aborda a síntese e investigação de estruturas nanométricas de Alumina Anódica Porosa AAP produzidas a partir de substratos de baixa pureza, com a finalidade da obtenção de membranas auto-suportadas. Foram utilizados os processos de Hard Anodization (HA) e Mild Anodization (MA). Para efeito comparativo entre os processos foram mantidas todas as condições variando apenas o potencial aplicado. Posteriormente para HA o tempo experimental foi reduzido pela metade a fim de investigar a velocidade no crescimento do óxido e condições de anodização de membranas sobre as amostras de vidro. Este trabalho também abrange a construção de um sistema Phisical Vapor Deposition (PVD) por evaporação térmica resistiva, capaz de evaporar metais com pontos de fusão abaixo de 800°C. Através da deposição de sucessivas camadas foi possível a obtenção de filmes metálicos de Alumínio com espessuras acima de 10 µm, possibilitando condições de síntese de alumina anódica porosa sobre substratos produzidos por evaporação térmica resistiva. O resultado da síntese de membranas em substratos de Al de baixa pureza foi complementar à síntese das membranas obtidas em alumínio evaporado em substratos de vidro, pois a espessura de cada filme depositado é baixa se comparados a espessura da camada de AAP. Portanto, houve a necessidade de várias deposições sobre as mesmas amostras, para se obter o filme de alumínio que fosse capaz de suportar uma camada de alumina anódica porosa resistente e que se aproximasse das características das obtidas pelo processo de MA. Todas as amostras anodizadas foram caracterizadas por microscopia eletrônica de varredura, inclusive as amostras produzidas a partir do alumínio metalizado. As micrografias obtidas a partir das membranas de alumínio de baixa pureza foram tratadas pelo software ImageJ, possibilitando a análise morfológica das mesmas. As membranas de AAP de baixa pureza possuem poros com ramificações transversais, são provocadas pelos desvios do campo elétrico aplicado, além da possibilidade de formação de outros tipos de óxidos. O filme de alumínio metalizado teve maior espessura nas amostras posicionadas na parte central do porta amostra, isso pode estar relacionado com o aquecimento do filamento que ocorre da região central para as extremidades. / 2010/10813-0