Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

The increasing number of mobile devices challenges the current radio frequency (RF) networks. The conventional RF spectrum for wireless communications is saturating, motivating to develop other unexplored frequency bands. Light Fidelity (LiFi) which uses more than 300 THz of the visible light spectrum for high-speed wireless communications, is considered a promising complementary technology to its RF counterpart. LiFi enables daily lighting infrastructures, i.e. light emitting diode (LED) lamps to realise data transmission, and maintains the lighting functionality at the same time. Since LiFi mainly relies on line-of-sight (LoS) transmission, users in indoor environments may experience blockages which significantly affects users' quality of service (QoS). Therefore, hybrid LiFi and RF networks (HLRNs) where LiFi supports high data rate transmission and RF offers reliable connectivity, can provide a potential solution to future indoor wireless communications. In HLRNs, efficient load balancing (LB) schemes are critical in improving the traffic performance and network utilisation. In this thesis, the optimisation-based scheme (OBS) and the evolutionary game theory (EGT) based scheme (EGTBS) are proposed for load balancing in HLRNs. Specifically, in OBS, two algorithms, the joint optimisation algorithm (JOA) and the separate optimisation algorithm (SOA) are proposed. Analysis and simulation results show that JOA can achieve the optimal performance in terms of user data rate while requiring high computational complexity. SOA reduces the computational complexity but achieves low user data rates. EGTBS is able to achieve a better performance/complexity trade-off than OBS and other conventional load balancing schemes. In addition, the effects of handover, blockages, orientation of LiFi receivers, and user data rate requirement on the throughput of HLRNs are investigated. Moreover, the packet latency in HLRNs is also studied in this thesis. The notion of LiFi service ratio is introduced, defined as the proportion of users served by LiFi in HLRNs. The optimal LiFi service ratio to minimise system delay is mathematically derived and a low-complexity packet flow assignment scheme based on this optimum ratio is proposed. Simulation results show that the theoretical optimum of the LiFi service ratio is very close to the practical solution. Also, the proposed packet flow assignment scheme can reduce at most 90% of packet delay compared to the conventional load balancing schemes at reduced computational complexity.

Compte tenu de la multiplication des standards dans le domaine des télécommunications,l’accordabilité au sein des systèmes est devenue une priorité en termes d’intégration et de coût.Un seul circuit accordable doit ainsi permettre d’adresser plusieurs normes. Dans la gamme deshyperfréquences, en technologie planaire, la fonction accordable (filtre ou antenne) estactuellement un dispositif passif distribué sur lequel sont reportés un ou plusieurs élémentsd’accords. Il est ainsi possible de faire varier au moins une des caractéristiques du dispositif(fréquence centrale et/ou bande passante pour les filtres et fréquence de résonance, diagrammede rayonnement ou mode de polarisation pour les antennes). Le circuit passif étant distribué, pourassurer la propagation de l’onde, un matériau diélectrique faible pertes est généralement utilisé.Cependant, l’ajout d’éléments d’accord engendre des pertes et des perturbations liées au report ducomposant (éléments parasites au niveau de l’interconnexion et des discontinuités composantd’accord-dispositif passif, et de la mise en boitier du composant reporté). Enfin, cette manière deréaliser des fonctions accordables rend peu flexible la conception (dimensions et localisation ducomposant d’accord) et la fabrication (perçage et métallisation pour les vias).Dans ce contexte, nous proposons de co-concevoir des fonctions hyperfréquences accordablessur un substrat semi-conducteur sur lequel il est à la fois possible de réaliser le composantd’accord et le dispositif passif distribué. Cette co-conception du circuit passif et de son élémentd’accord permet d’éliminer toutes les contraintes liées au report de composant, au perçage de viamétallique et apporte une grande flexibilité au niveau du dimensionnement de la zone dopée. Eneffet, elles peuvent être soit localisées soit distribuées. Toutefois, ce concept nécessite que lesupport semi-conducteur soit à la fois compatible à la propagation de l’onde et à la réalisation del’élément d’accord. Ces travaux de thèse ont permis de lever ce verrou en proposant descompromis permettant la réalisation de composants accordables validés par des démonstrateurssur technologie silicium.Au cours de ces travaux, une ligne de transmission micro-ruban et un composant d’accord de typeswitch ont été co-conçus. De très bonnes performances, validées par la mesure, ont été obtenues.De plus, une démarche de co-simulation a été proposée pour prendre en compte les effets semiconducteursdans la simulation électromagnétique.Le concept ayant été validé, il a été ensuite appliqué à des dispositifs accordables relativementsimples afin de montrer le potentiel de cette démarche (en termes de performances et de flexibilitéde conception), tels que des filtres accordables, des guides d’ondes de type SIW (SubstrateIntegrated Waveguide) reconfigurables ou encore des antennes accordables en fréquence. Cestravaux font également apparaître de nombreuses perspectives pour la réalisation de nouvellestopologies de filtres accordables (filtres SIW, interdigités…), d’antennes accordables (enfréquence, en diagramme de rayonnement…) ou de déphaseurs. Enfin, un potentiel a été identifiépour de nouvelles topologies de fonctions accordables en continu à base de jonction de typediodes varactors (composants à capacités variables). / Given the proliferation of standards in telecommunication systems, tunability is becoming a priorityboth in terms of integration and cost. A single tunable circuit needs to be able to work according toseveral different standards. Nowadays, a tunable function (filter or antenna) in planar technology isa passive distributed device to which some active tuning elements are soldered. At least onecharacteristic of the device can therefore be varied (the central frequency and/or the bandwidth inthe case of a filter; or the resonant frequency, radiating pattern or polarization mode in the case ofan antenna). Because passive devices are distributed in order to propagate the electromagneticwave, they are often designed on a dielectric substrate to minimize losses. However, the additionof tuning elements causes some additional losses and disturbances (some parasitic effects canarise due to the packaging or the interconnection and discontinuities between active and passiveparts). Finally, these tunable functions reduce the flexibility of the design (due to the size andlocalization of the active tuning elements) and manufacturing (due to drilling and via metallization).In this context, we propose to co-design tunable microwave functions on a semiconductorsubstrate on which it is possible to build both the tunable element and the passive distributedcomponent. This co-design between the passive and active parts removes the constraints relatedto the tuning elements and drilling of via holes. The concept offers a greater flexibility with regard tothe size of doped areas, allowing them to be either localized or distributed. However, this approachrequires the substrate to be compatible with the propagation of the electromagnetic field and withthe design of the tunable element. The work of this thesis makes it possible to overcome suchobstacles by proposing some tradeoffs allowing the design and the manufacture of tunablemicrowave components in silicon technology, which have been validated by demonstrator circuits.During this work, a microstrip transmission line and a switch were co-designed. Goodperformances were obtained both in simulations and measurements. Moreover, a co-simulationapproach is proposed to take into account the semiconductor effects in electromagneticsimulations.Once validated, this concept was applied to other relatively simple tunable devices to show thepotential of this approach (in terms of performances and design flexibility). Applications includedtunable filters, reconfigurable waveguides (such as SIW: Substrate Integrated Waveguides) andfrequency-tunable antennas. This study showed promising results for the design of new tunablefilter topologies (SIW filters, coupled-line filters), tunable antennas (in resonant frequency orradiation pattern) and phase shifters. Finally, the approach shows potential for continuous tunablefunctions based on varactor diodes (with capacitance variation).

Experimentos de Imagens por Ressonância Magnética (IRM) em pequenos animais, assim como em humanos, exigem um conjunto especifico de bobinas de Radiofrequência (RF) para maximizar ambos a homogeneidade de campo durante a transmissão e a Relação Sinal Ruído (RSR) durante a recepção. As geometrias mais comuns de bobinas transmissoras utilizadas em sistemas de humanos são as bobinas tipo gaiola ou Birdcage Coil. Dentre as geometrias de bobinas receptoras, o conceito de bobina tipo Phased Array é amplamente utilizado em aplicações que necessitam de alta RSR em uma grande região de interesse, além de permitirem obter imagens com metodologias de aquisição paralela. Este trabalho descreve o desenvolvimento de um conjunto de bobinas transmissoras e receptoras especificamente projetadas para a aquisição de imagens do cérebro de ratos para o estudo do hipocampo. As geometrias de bobinas transmissoras estudadas foram dois Birdcages com 8 e 16 condutores e a geometria proposta por nós chamada Double Crossed Saddle (DCS Coil). Para a recepção desenvolvemos uma bobina de superfície com dois loops e um Phased Array com dois canais de recepção. Os resultados confirmam que dentre as bobinas transmissoras desenvolvidas a geometria do tipo Birdcage com 16 condutores é a mais homogênea, produzindo campos de RF com alta uniformidade em regiões de interesse de até 80% do diâmetro interno das bobinas. No entanto, o elevado número de capacitores em sua estrutura faz com que a geometria DCS coil, devido à sua simplicidade e reduzido número de capacitores, represente uma alternativa em experimentos onde as condições de carga da amostra possam variar. Dentre as geometrias de receptoras estudadas a bobina de superfície obteve maior desempenho em termos de RSR em comparação com o Phased Array de 2 canais. A comparação dos resultados utilizando bobinas específicas para a transmissão e recepção com uma bobina volumétrica operando como transmissora e receptora simultaneamente comprova a superioridade em termo de RSR dos sistemas que utilizam bobinas dedicadas, sendo confirmados através de imagens in vivo do cérebro de ratos, possibilitando aquisições com mesma resolução e RSR em um tempo reduzido de experimento. / Magnetic Resonance Imaging (MRI) experiments on small animals, as well as in human, require a specific RF coil set in order to maximize the Radiofrequency (RF) field homogeneity during transmission and Signal-to-Noise Ratio (SNR) during reception. The most common geometries of RF transmitter coil used in human systems are the well known Birdcage resonators. Among the receiver coils geometry the concept of NMR Phased Arrays or multi channel coils is widely employed in applications that need a high SNR in a large region of interest (ROI), further allowing parallel imaging acquisition methodologies. The work reported here describes the development of a transmit-only and receive-only RF coil set actively detuned specifically designed to MRI acquisition of rats brain for purposes of neuroscience studies. The transmitter geometries developed were two Birdcages with 8 and 16 rungs and our proposed geometry named Double Crossed Saddle (DCS). For reception we developed one common surface coil made of two turn loops and a 2-channel Phased Array, both actively detuned during reception. The results have confirmed that the 16 rungs Birdcage are superior among other transmit coils in producing homogeneous RF field inside a ROI of 80% of coil´s inner diameter. However, the simplicity and reduced number of capacitors makes the DCS coil a good choice in experiments with different samples and load conditions. Among the receive coils developed, the surface coil showed a better SNR in comparison with the 2-channel Phased array, which has the advantage of producing a large area with high SNR. The SNR of both surface coil and 2-channel array was compared with a transceiver Saddle Crossed coil, available at our lab, specific designed to obtain rat brain images. These results have corroborated that transmit-only and receive-only RF coils have best performance than transceiver volume coils for obtain MRI images of rats brain, allowing image acquisition with same resolution and reduced scan time.

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these analog/RF systems are implemented in scaled nanometer nodes. At these nodes, the high level of variability in process variations is making the task of manufacturing high fidelity systems a challenge leading to yield and reliability issues. Hence, in the post-manufacturing phase, test and diagnosis steps are critical to identify the cause and effect of the process variations. Further, intelligent post-manufacturing tuning techniques are required to correct the effect of process variations on analog/RF systems. In this work, a die-level concurrent test and diagnosis approach using optimized measurements obtained in high volume manufacturing environment is proposed for analog/RF circuits. Such a simultaneous test and diagnosis methodology enables monitoring parametric process shifts and providing rapid feedback to the fab to minimize or prevent yield loss. In the case of devices that are continuously operating in the field, an efficient on-line diagnosis approach has been developed to perform reliability related prognosis. For advanced RF technologies such as MIMO-OFDM systems, a rapid system-level testing scheme is presented that performs concurrent testing of the multiple RF chains. Depending on the availability of the computational resources and system tuning knobs, different low-cost methodologies for post-manufacture tuning or self-healing of RF SISO/MIMO systems are developed. These include faster digital monitoring and tuning techniques, on-chip tuning techniques using digital logic that enables die-level self-tuning, and DSP-based power conscious iterative techniques for SISO/MIMO RF systems. An adaptive power-performance tuning technique is developed for those devices that have a post-manufacture power consumption value that is more than the acceptable limit. These intelligent post-manufacturing techniques result in reduced manufacturing cost, improved yield, and reliability of analog/RF systems.

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs. / text

This thesis concerns the introduction and development in our laboratory of a multilayer ceramic technology, called LTCC, for RF and microwave packaging. LTCC stands for Low Temperature Co-fired Ceramics. As can be understood from its name, the low temperature means that the LTCC circuit is fired below 1000 °C that allows the use of high conductivity materials such as gold and silver. The thesis work starts after the bibliographic study of RF packaging technology, with the choice of LTCC substrate and conductor materials necessary to implement LTCC technology in our laboratory. Then, the LTCC manufacturing process is put in place and validated in order to produce operational LTCC circuits. This process includes the cut of LTCC layers, via hole and cavity creation, via fill for vertical interconnecting, screen printing for horizontal patterns, stacking, lamination and finally the firing to obtain a 3D circuit. Most encountered technological problems are resolved and the fabrication steps are validated. LTCC DESIGN RULES that contain all dimensional values required for future RF packaging designers at the laboratory is elaborated. Next, after the successful establishment of LTCC technology, it is qualified up to 40 GHz using simple RF structures such as transmission lines and planar resonators. Then, a multilayer LTCC package for an MMIC oscillator functioning in the frequency band between 10.6 and 12.6 GHz is proposed, fabricated and finally measured.

Cell biological exposure studies in magnetic resonance imaging (MRI) environment, where a complex mixture of strong magnetic fields are present, have attracted considerable interest in recent years. The outcome of such studies might depend strongly on the conditions, for example exposure parameters and spatial variations of exposure. The aim of this thesis has been to give a detailed description of how the radio frequency (RF) magnetic field varies with position and sequence choice within an MRI bore from a patient perspective and to highlight the need of better consistency in future research. Method: A straightforward theoretical description on the contribution to the RF magnetic field from a birdcage coil is given. A one dimensional coaxial loop antenna has been used as a probe to measure spatial variations of the RF magnetic field in a 1.5T MRI scanner. An exposure matrix containing RF magnetic field strength (H1-field) amplitudes in three dimensions was constructed and used to study several clinical protocols and sequences. A qualified correspondence measurement was also made on a 3T MRI scanner. Results: Around isocenter, for a common field-of-view (FOV), changes in exposure conditions were small; however, rapid changes of exposure conditions occurred upon approaching the end rings. The dominating H1-field component switched from lying in the xy-plane to pointing the z-direction and was roughly 3 times larger than in isocenter. Practical difficulties indicate even larger differences at positions not measurable with the equipment at hand. The strongest H1-field component was 32.6 A/m at position (x,y,z)=(-24,8,24) cm from the isocenter. Conclusions: Machine parameters such as repetition time, echo time and flip angle have little to do with actual exposure. Specic absorption rate (SAR) values correlated well with the square of measured root-mean-square (RMS) values of the magnetic field (B1,RMS) but not with peak values of the magnetic field (B1,peak), indicating that peak values are not unlikely to be part of compromising factors in previous contradictory exposure research on genotoxicity. Furthermore exposure conditions depend strongly on position and unfavorable situations may occur in the periphery of the birdcage coil. Potentially elevated risks for conducting surfaces, for example arms or external fixations, in the proximity of the end rings, are proposed. Aside from spatial variation consideration on which type of geometry exposed cell-biological samples are placed in should be held since eddy currents, hot-spots and proper SAR depend on geometry. Conditions may vary considerably between in-vitro, ex-vivo and in-vivo studies since geometries of test tubes, petri dishes and humans differ.