Arbeitsübersetzung aus dem Russischen (Volltext), Angefügt die Originalfassung in Russisch (Volltext), Militärdoktrin der Russischen Föderation vom November 1993.:Vorbemerkungen der Übersetzer. Arbeitsübersetzung (deutsch): Die Militärdoktrin der Russischen Föderation I. Militärpolitische Grundlagen. II. Militärstrategische Grundlagen. III. Militärökonomische Grundlagen. Anhang: - Russische Originalfassung der Militärdoktrin der Russischen Föderation. - Begriffsklärungen: Andere Truppen, Militärische Formationen, Militärische Organe.

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Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1x1x2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.

A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation

Implantable biomedical wireless sensors provide monitoring of vital health signs such as oxygen, temperature and intraocular pressure and may help to analyse and detect diseases in humans and animals. However, one of the design challenges of implantable devices is providing a safe and reliable energy source. Replaceable batteries are one of the most common methods for powering up implantable devices and have been used in e.g.cardiac pacemakers for decades. However, the need for a regular battery replacement may require surgical incisions. Multiple studies have been done on energy harvesting from ambient energy sources to provide the required power for the operation of the implantable sensor and thus reducing the need for battery replacement. In this work, a circuit-level radio frequency (RF) energy harvesting system has been designed and simulated in 65 nm CMOS process technology. The system consists of an AC-DC converter, a DC-DC converter, a Ring oscillator, a Buffer, and a Voltage sensor with comparators, dividers and a reference generator. The rectifier operates at a frequency of 900 MHz and offers a power conversion efficiency (PCE) of 71%. The doubler works at 50 MHz with a voltage conversion efficiency (VCE) of 98%. Additionally, the Voltage sensor monitors the voltage level of the energy-storing unit, that in this project is intended to be an mm-size rechargeable battery. If the voltage level is equal to or higher than a threshold value, Vref, the harvesting system will be in discharging mode. Similarly, if the voltage level is below Vref, then the system will be in charging mode.

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QC 20100622

Silicon-on-Insulator (SOI) CMOS technology constitutes a good candidate for mixed signal RF CMOS applications. Due to its low junction capacitance and reduced leakage current, SOI provides reduced static and dynamic power consumption of the digital logic combined with increased cut-off frequencies. Moreover, in terms of passive device integration the major benefit of SOI when compared to the conventional bulk is the possibility to use a high resistivity substrate which allows a drastic reduction of substrate losses allowing a high quality factor of the passive devices. Another issue is the harsh environment applications. Electronics capable of operating at high temperatures are required in several industrial applications, including the automobile industry, the aerospace industry, the electrical and nuclear power industries, and the well-logging industry. The capability of SOI circuits to expand the operating temperature range of integrated circuits up to 300°C has been demonstrated. SOI devices and circuits present advantages in this field over bulk counterparts such as the absence of thermally-activated latch up and reduced leakage current. In this context, various topologies of integrated transmission lines and spiral inductors implemented on standard and high substrate resistivities have been analyzed over a large temperature range. The temperature behavior of the SOI transistors is presented. The main figures-of-merit of the SOI MOSFETs are analyzed and the extraction of the extrinsic and intrinsic parameters of the small signal equivalent circuit is performed. Also, an example of RF circuit applications of the SOI technology, based on a fully integrated Low-Noise Amplifier for low-power and narrow-band applications, is investigated and characterized at high temperature. The main figures-of-merit of the designed circuit are extracted and discussed. The good results show that the SOI technology is now emerging as a good candidate for the realization of analog integrated circuits for low-power and high-temperature applications.

Le développement des systèmes multiprocesseurs intégrés sur puce (MPSoC) répond au besoin grandissant des architectures de calcul intensif. En revanche, l'évolution de leurs performances est entravée par leurs réseaux de communication sur puce (NoC) à cause de leur consommation d'énergie ainsi que du retard. C'est dans ce contexte que les NoC à base d'interconnexions RF et filaires (RFNoC) ont émergé. Afin de gérer au mieux et d'optimiser la conception d'un RFNoC, il est indispensable de développer une plateforme de simulation intégrant à la fois des circuits analogiques et numériques.Dans un premier temps, la simulation temporelle d'un RFNoC avec des composants dont les modèles sont idéaux est utilisée pour optimiser l'allocation des ressources spectrales disponibles. Le cas échéant, nous proposons des solutions pour améliorer la qualité de signal transmis. Dans un deuxième temps, nous avons développé en VHDL-AMS des modèles comportementaux et précis de chacun des composants du RFNoC. Les modèles de l'amplificateur faible bruit (LNA) et du mélangeur, prennent en compte les paramètres concernant, l'amplification, les non-linéarités, le bruit et la bande passante. Le modèle de l'oscillateur local considère les paramètresconventionnels, notamment le bruit de phase. Quant à la ligne de transmission, un modèle fréquentiel précis, incluant l'effet de peau est adapté pour les simulations temporelles. Ensuite, l'impact des paramètres des composants sur les performances du RFNoC est évalué afin d'anticiper les contraintes qui s'imposeront lors de la conception du RFNoC. / The development of multiprocessor systems integrated on chip (MPSoC) respondsto the growing need for intensive computation systems. However, the evolutionof their performances is hampered by their communication networks on chip(NoC) due to their energy consumption and delay. It is in this context that the wired RF network on chip (RFNoC) was emerged. In order to better manage and optimize the design of an RFNoC, it is necessary to develop a simulation platform adressing both analog and digital circuits.First, a time domaine simulation of an RFNoC with components whose modelsare ideal is used to optimize the allocation of the available spectrum resources. Where appropriate, we provide solutions to improve the quality of transmitted signal. Secondly, we have developed, in VHDL-AMS, behavioral and accurate models of all RFNoC components. The models of the low noise amplifier (LNA) and the mixer take into account the parameters for the amplification, nonlinearities, noise and bandwidth. The model of the local oscillator considers the conventional parameters, including its phase noise. Concerning the transmission line, an accurate frequency model, including the skin effect is adapted for time domaine simulations. Then, the impact of component parameters on RFNoC performances is evaluatedto anticipate constraints of the RFNoC design.