Gallium Nitride (GaN) high electron mobility transistors (HEMT) have superior performance characteristics compared to Silicon (Si) and Gallium Arsenide (GaAs) based transistors. GaN is a wide bandgap semiconductor which allows it to operate at higher breakdown voltages and power. Unlike traditional semiconductor devices, the GaN HEMT channel region is undoped and relies on the piezoelectric effect created at the GaN and Aluminum Gallium Nitride (AlGaN) heterojunction to create a conduction channel in the form of a quantum well known as the two dimensional electron gas (2DEG). Because the GaN HEMTs are undoped, these devices have higher electron mobility crucial for high frequency operation. However, over time and use these devices degrade in a manner that is not well understood. This research utilizes low frequency noise (LFN) as a method for analyzing changes and degradation mechanisms in GaN-on-Si devices due to gate stress. LFN is a useful tool for probing different regions of the device that cannot be measured through direct means. LFN generation in GaN HEMTs is based on the carrier fluctuation theory of 1/f noise generation which states fluctuations in the number of charge carriers results in conductance fluctuations that produce a Lorentzian noise spectrum. The summing Lorentzian noise spectra from multiple traps leads to 1/f and random telegraph signal (RTS) noise. The primary cause of carrier fluctuations are electron traps near the 2DEG and in the AlGaN bulk. These traps occur naturally due to dislocations and impurities in the manufacturing process, but new traps can be generated by the inverse-piezoelectric effect during gate stress. This thesis introduces noise and presents a circuit to bias the devices and measure gate and drain LFN simultaneously. Three measurements are performed before and after gate DC stress at three different temperatures: DC characterization, capacitance-voltage (C-V) measurements, and LFN measurements. The DC characteristics show an increase in gate leakage after stress caused by an increase in traps after degradation consistent with trap assisted tunneling. However, the leakage current on the drain and source side differ before and after stress leading to the conclusion that the source side of the gate is more sensitive to gate stress. Gate leakage current on the drain side is also sensitive to temperature due to thermionic trap assisted tunneling. Hooge parameter calculations agree with previous research. The LFN results show an increase in gate and drain noise power, SIg(f) and SId(f), in accordance with increased gate leakage current under cutoff bias. RTS noise is also observed to increase in frequency with increased temperature. Activation energies for RTS noise are extracted and qualitatively linked to trap depth based on the McWhorter trap model.

The mode-locked laser diode (MLLD) finds a lot of use in applications such as ultra high-speed data processing and sampling, large-capacity optical fiber communications based on optical time-division multiplexing (OTDM) systems. Integrating mode-locked lasers on silicon makes way for highly integrated silicon based photonic communication devices. The mode-locked laser being used in this thesis was built with Hybrid Silicon technology. This technology, developed by UC Santa Barbara in 2006, introduced the idea of wafer bonding a crystalline III- V layer to a Silicon-on-insulator (SOI) substrate, making integrated lasers in silicon chips possible. Furthermore, all mode-locked lasers produce phase noise, which can be a limiting factor in the performance of optical communication systems, specifically at higher bit rates. In this thesis, we design and discuss an impedance matching solution for a hybrid silicon mode-locked laser diode to lower phase noise and reduce the drive power requirements of the device. In order to develop an impedance matching solution, a thorough measurement and analysis of the impedance of the MLLD is necessary and was carried out. Then, a narrowband solution of two 0.1 pF chip capacitors in parallel is considered and examined as an impedance matching network for an operating frequency of 20 GHz. The hybrid silicon laser was packaged together in a module including the impedance- matching circuit for efficient RF injection. In conclusion, a 6 dB reduction of power required to drive the laser diode, as well as approximately a 10 dB phase noise improvement, was measured with the narrow-band solution. Also, looking ahead to possible future work, we discuss a step recovery diode (SRD) driven impulse generator, which wave-shapes the RF drive to achieve efficient injection. This novel technique takes into account the time varying impedance of the absorber as the optical pulse passes through it, to provide optimum pulse shaping.

It is well known that real op-amps do not share most of the desirable characteristics of an ideal one, particularly those of gain and output impedance. When presented with a capacitive load, such as a MOSFET or ADC, feedback in an op-amp circuit can quickly become unstable. This thesis studies and characterizes an op-amp’s output impedance and how its interaction with this type of load creates a parasitic pole which leads to instability. Applying ideas from feedback control theory, a model for studying the problem is developed from which a generalized method for compensating the undesirable circumstance is formulated. Even in a zero-input state, many real op-amps driving capacitive loads can experience unforced oscillations. A case study is performed with three commonly used devices. First, the output impedance is determined by its dependence on the unity-gain bandwidth, load capacitance, and oscillation frequency. It is fitted into a second-order feedback control model that allows for an analytical study of the problem. It is then shown that a carefully designed passive network can be introduced between the load and op-amp to obtain a properly damped system free of oscillation and well-behaved. Using a shunt resistor is a known and commonly used method for lowering an op-amp’s output impedance to gain stability. This work considers the converse addition of a series capacitor to instead lower the load capacitance seen by the op-amp, a seemingly complementary method that achieves the same goal. A generalized, composite compensation method is developed that uses both the shunt resistor and series capacitor– a strategy not yet found in literature. Relevant formulas for damping ratio and natural frequency are derived that allow the design of a passive compensation network. Furthermore, tradeoffs between compensation, voltage swing, current consumption, and power usage are considered. An emphasis is placed on comparing simulated versus real circuits to highlight the fact that any problem is much worse in real-life than in a simulation. SPICE models and programs aim to de-idealize certain device characteristics, but often cannot account for environmental conditions and manufacturing variance. Thus, an importance is placed on experimental verification guided by simulations.

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Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However, calibration requires going through temperature steps in a tester, increasing test application time and cost. Consequently, calibrating thermal sensors in typical digital designs including mainstream desktop and notebook processors increases the cost of the processor. This creates a need for design of thermal sensors whose accuracy does not vary significantly with process variations. Other qualities desired from thermal sensors include low area requirement so that many of them maybe integrated in a design as well as low power dissipation, such that the sensor itself does not become a significant source of heat. In this work, we developed a process variation tolerant thermal sensor design with (i) active compensation circuitry and (ii) signal dithering based self calibration technique to meet the above requirements in 32nm technology. Results show that we achieve 3ºC temperature accuracy, with a relatively small design which compares well with designs that are currently used.

This thesis describes an accurate and scalable computational method designed to perform nanoelectronic structure calculations. Built around the FEAST framework, this method directly addresses the nonlinear eigenvalue problem. The new approach allows us to bypass traditional approximation techniques typically used for first-principle calculations. As a result, this method is able to take advantage of standard muffin-tin type domain decomposition techniques without being hindered by their perceived limitations. In addition to increased accuracy, this method also has the potential to take advantage of parallel processing for increased scalability. The Introduction presents the motivation behind the proposed method and gives an overview of what will be presented for this thesis. Chapter 1 explains how electronic structure calculations are currently performed, including an overview of Density Functional Theory and the advantages and disadvantages of various numerical techniques. Chapter 2 describes, in detail, the method proposed for this thesis, including mathematical justification, a matrix-level example, and a description of implementing the FEAST algorithm. Chapter 3 presents and discusses results from numerical experiments for Hydrogen and various Hydrogen molecules, Methane, Ethane, and Benzene. Chapter 4 concludes with a summary of the presented work and its impact in the field.

Over the last five years, charge-coupled devices (CCD) have been improved dramatically in terms of sensitivity, manufacturability and particularly, cost. This has enabled them to be used economically in many more industrial and commercial electronic imaging processes. They are found in products ranging from video cameras to satellite-based camera systems. This has sparked my interests in these devices, and with a great deal of encouragement from Dr. Turpin, I decided to base my Master's thesis/project on a CCD. The project was mainly based on the design of the electronics and optics needed to support a CCD. The particular circuit design which I used other designs which are available. Many of the designs are microprocessor- based, which tends to limit the speed of operation of the imaging process. Other circuits employ specially coded memory chips to implement the required logic processes, but again, the speed of operation is limited by the access times of the memory chips. The circuit employed in the project uses only logic gates and flip flops, and is probably one of the fastest circuits available for the capture of single-frame images.

Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design and simulation of a ring oscillator that exhibits the frequency modulated signal on a single integrated circuit chip. The ring oscillator is controlled by a voltage ramp signal generator and a voltage to current (V-I) converter. The circuit is designed in Cadence using TSMC 180nm process technology and operates in the frequency range of 3.409 GHz to 5.349 GHz with a spectral bandwidth of 1.94 GHz, which meets the Federal Communications Commission’s standards for unlicensed ultra-wideband transmissions.

The number of mobile wireless devices on the market has increased substantially over the last decade. The frequency spectrum has become crowded due to the number of devices demanding radio traffic and new modulation schemes have been developed to accommodate the number of users. These new modulation schemes have caused very poor efficiencies in power amplifiers for wireless transmission systems due to high peak-to-average power ratios (PAPR). This thesis first presents the issue with classical power amplifiers in modern modulation systems. A brief overview of current attempts to mitigate this issue is provided. A new RF power amplifier topology is then presented with supporting simulations. The presented amplifier topology utilizes the concept of negative conductance and load modulation. The amplifier operates in two stages, a low power stage and a high power stage. A negative conductance amplifier is utilized during peak power transmission to modulate the load presented to the input amplifier. This topology is shown to greatly improve the power added efficiency of power amplifiers in systems with high PAPR.

Printed Circuit Boards (PCBs) are a ubiquitous element of virtually every electronic system manufactured world-wide. It is not a stretch of the imagination to say that if it’s electronic, there is a PCB in it. PCBs are necessary tools for electronics work, and tools need to have instructions. For better or worse, PCB knowledge is a deep and wide ocean. There is much to cover for even a surface level understanding, and there are deep areas rich in technical expertise. Navigating the ocean of knowledge is treacherous; common knowledge of yore can be downright dubious now. PCB manufacturing and electronics as a whole have seen incredible developments in the past few decades, and knowledge once true may be outdated. At the same time there is a downpour of new techniques to use and challenges to face. The storm of information deepens the sea and can make it seem impossible to get anywhere without getting utterly lost. There are islands of knowledge out there hiding in books and papers and websites, but no guide to get anywhere. This thesis aims to guide the reader through the sea of information and provides a map that charts the shallows of beginner knowledge, into the deep depths of advanced design, of how and where to learn more. This thesis serves as an aiding means through the exciting and vast world of PCB design and layout.