As the scaling of CMOS approaches fundamental limits, revolutionary technology beyond the end of CMOS roadmap is essential to continue the progress and miniaturization of integrated circuits. Recent research efforts in 3-D circuit integration explore pathways of continuing the scaling by co-designing for device, circuit, connectivity, heat and manufacturing challenges in a 3-D fabric-centric manner. SkyBridge fabric is one such approach that addresses fine-grained integration in 3-D, achieves orders of magnitude benefits over projected scaled 2-D CMOS, and provides a pathway for continuing scaling beyond 2-D CMOS. However, SkyBridge fabric utilizes only single type transistors in order to reduce manufacture complexity, which limits its circuit implementation to dynamic logic. This design choice introduces multiple challenges for SkyBridge such as high switching power consumption, susceptibility to noise, and increased complexity for clocking. In this thesis we propose a new 3-D fabric, similar in mindset to SkyBridge, but with static logic circuit implementation in order to mitigate the afore-mentioned challenges. We present an integrated framework to realize static circuits with vertical nanowires, and co-design it across all layers spanning fundamental fabric structures to large circuits. The new fabric, named as SkyBridge-CMOS, introduces new technology, structures and circuit designs to meet the additional requirements for implementing static circuits. One of the critical challenges addressed here is integrating both n-type and p-type nanowires. Molecular bonding process allows precise control between different doping regions, and novel fabric components are proposed to achieve 3-D routing between various doping regions. Core fabric components are designed, optimized and modeled with their physical level information taken into account. Based on these basic structures we design and evaluate various logic gates, arithmetic circuits and SRAM in terms of power, area footprint and delay. A comprehensive evaluation methodology spanning material/device level to circuit level is followed. Benchmarking against 16nm 2-D CMOS shows significant improvement of up to 50X in area footprint and 9.3X in total power efficiency for low power applications, and 3X in throughput for high performance applications. Also, better noise resilience and better power efficiency can be guaranteed when compared with original SkyBridge fabrics.

<p>We propose a physically based model that describes the density and size of voids in silicon introduced via high dose helium ion implantation and subsequent annealing. The model takes into account interactions between vacancies, interstitials, small vacancy clusters, and voids. Void evolution in silicon occurs mainly by a migration and coalescence process. Various factors such as implantation energy and dose, anneal temperature, atmospheric pressure, and impurity level in silicon can influence the migration and coalescence mechanism and thus play a role in the void evolution process. Values for model parameters are consistent with known values for point defect parameters and assumed diffusion limited reaction rates. A single “fitting parameter” represents the rate of bubble migration and coalescence and is therefore related to surface diffusion of adatoms. Results obtained from simulations based upon the model were compared to our experimental results and to previously reported experimental results obtained over a wide range of conditions.</p> <p>Our own experiments involved the implantation of silicon samples and samples with a thin Si_1-xGe_x (x = 0.05, 0.09) epilayer on silicon with 30 keV, 5×10¹⁶ cm^-2 helium. Anneals were done in the range 960-1110°C for 15-30 minutes in nitrogen and dry oxygen. Void size distributions were measured from transmission electron microscopy images. Average void diameter and void density values and void size distribution did not show any significant differences between the samples annealed in nitrogen and dry oxygen. However, the presence of Si_1-xGe_x epilayer on silicon resulted in increased average void diameter and reduced average void density when compared with Si samples as well as more selective void size distribution.</p> <p>Data from the literature included experiments with helium ion implantation energies in the range 30 - 300 keV, doses of 1×10¹⁶ - 1×10¹⁷ cm^-2, subsequent annealing temperatures in the range 700 - 1200°C, and annealing duration in the range 15 minutes - 2 hours. Excellent agreement is found between the simulated results and those from reported experiments. The extracted migration and coalescence rate parameter shows an activation energy consistent with surface diffusivity of silicon. It shows a linear dependence on helium dose, and increases with decreased implantation energy, decreased ambient pressure, decreased substrate impurities, increased temperature ramp rate, or increased Ge fraction in cavity layer, all consistent with the proposed physical mechanism. Our mathematical model specifically ignores the long time saturation in void size, although we propose a simple explanation consistent with the physical picture. Similarly, we give physical reasons for a threshold implant dose resulting in the formation of small vacancy clusters during implant. But in modeling void growth we simply show that when such clusters exist voids will evolve according to our model.</p> <p>In our experiments, the presence of a Si_0.95Ge_0.05 epilayer on silicon resulted in retarded B diffusion when compared with Si samples. This phenomenon is correlated to the role of the Si_0.95Ge_0.05 epilayer on silicon in the void evolution mechanism and both are attributed to Ge interdiffusing from the epilayer into the Si bulk. The B diffusion data also allows us to predict conditions for the SiGe epilayer to modify the injection of interstitials from surface during dry oxidizing anneal.</p> / Doctor of Philosophy (PhD)

<p>A glass-clad, slow-light photonic-crystal waveguide is proposed as a solution to sub-bandgap light detection in silicon photonic circuits. Such detection in silicon is perceived as a challenge owing to silicon's indirect band gap and transparency to 1550nm wavelengths, yet is essential for achieving low-cost, high-yield integration with today's microelectronics industry. Photonic crystals can be engineered in such a way as to enhance light-matter interaction over a specific bandwidth via the reduction of the group velocity of the propagating wave (i.e. the slowing of light). The interaction enhanced for light detection in the present work is electron-hole pair generation at defect sites. The intrinsic electric field of a p-i-n junction enables light detection by separating the electron-hole pairs as a form of measurable current. The photonic-crystal waveguides are designed to have bandwidths in the proximity of a wavelength of 1550nm. Refractive indices of over 80 near the photonic-crystal waveguide's Brillouin zone boundary are measured using Fourier transform spectral interferometry and are found to correspond to numerical simulations. Defect-induced propagation loss was seen to scale with group index, from 400dB/cm at a group index of 8 to 1200dB/cm at a group index of 88. Scaling was sublinear, which is believed to be due to the spreading of modal volume at large group index values. Photodetectors were measured to have responsivities as high as 34mA/W near the photonic-crystal waveguide's Brillouin zone boundary for a reverse bias of 20V and a remarkably short detector length of 80um. The fabrication of each device is fully CMOS-compatible for the sake of cost-effective integration with silicon microelectronics.</p> / Master of Applied Science (MASc)

The performance of III-V heterojunction bipolar transistors (HBTs) has improved significantly over the past two decades. Today’s state of the art Indium Phosphide (InP) HBTs have a maximum frequency of oscillation greater than 800 GHz and have been used to realize an amplifier operating above 600 GHz . In comparison to silicon (Si) based devices, III-V HBTs have superior transport properties that enables a higher gain, higher speed, and noise performance, and much higher Johnson figure- of-merit . From this perspective, the InP HBT is one of the most promising candidates for high performance mixed signal electronic systems.

In recent years, there has been an explosion of advancements in artificial intelligence, especially in language models. These models have become essential in aiding and providing information for various tasks. This study explores five proprietary and open-source large language models (LLMs) and examines their reliability and accuracy in selecting parts and constructing connections of ten circuit design tasks from our benchmark. During our investigations, we assessed that the default textual outputs from these LLMs could lead to ambiguous responses that are either too general or open to multiple interpretations. To enhance clarity, we developed an artificial intelligence (AI)-based pipeline that translates responses from LLMs into netlists, eliminating the need for further training or fine-tuning. Our study aims to highlight the reliability and accuracy of the default responses, develop a solution that provides a more explicit netlist description, and compare default and netlist outputs.

The proposed research is for a novel SiGe-based Ion-Sensitive Dual Hetero-junction Bipolar Transistor (IS-HBT) to be used in both trans-dermal biological sensing as well as Lab-on-Chip (LOC) applications. The end goals for the device designed are two: For one, the research done for this work will be used to substantiate the claims made by Zafar et al. [1] that an HBT-style structure is better suited for biosensing application rather than a conventional Field Effect Transistor (FET) based geometries. Secondly, it provides the final element to be integrated along with a selectivity membrane, as well as with a reverse-iontophoresis system to enact trans-dermal sensing of potassium ions in a wearer’s body. The novelty of the device stems from the proposed modified wedding-cake structure lending itself to be easily implemented in a wearable package, the fact that it will act as both a transduction device as well as provide preamplification of signals. If successful, future researchers and/or corporations will have at their disposal a label-free advanced biosensor design that is integration-ready with currently available standard SiGe-BiCMOS processes.

Composants essentiels de tout ordinateur, les semi-conducteurs sont utilisés dans de nombreux secteurs. Les percées technologiques dans ce domaine imposent un rythme vertigineux aux industriels. Tous les deux ans environ, la capacité des puces est doublée et leur prix est divisé par deux. Le diamètre des plaquettes de silicium augmente et, regroupées en lots, les plaquettes sont plus lourdes à transporter. Les systèmes automatiques de transport (AMHS) se présentent comme une excellente alternative. Le prix très élevé des équipements de production fait que l’objectif est de saturer les capacités de production. Pour y parvenir, il est important que le système de transport et de stockage garantisse que les machines n’attendent pas des lots disponibles, et aussi que les lots n’attendent pas une machine disponible.Dans la littérature, la complexité du problème (jusqu’à 700 étapes de fabrication, flux réentrants, etc.) fait que les études de modélisation du transport se font avec de fortes hypothèses sur la production ou inversement. Pourtant, le transport est un service pour la production. Cette thèse propose une approche de modélisation permettant d'intégrer le plus fidèlement possible les contraintes de transport, production et stockage, afin d'améliorer les indicateurs clés de la production. Une analyse détaillée du système a permis de construire un modèle de simulation à événements discrets. Enfin, après une validation industrielle, l'étude complète du modèle a permis d'analyser les paramètres critiques de gestion du transport. Les résultats permettent une meilleure compréhension du système et mettent en exergue d'intéressantes perspectives de recherche. / Essential components of all computers, semiconductors are widely used in many sectors. Quick advances in these technologies force a challenging rhythm to manufacturers. Following the Moore’s Law, chip capacity doubles approximately every two years and prices are divided by two. Thus, the increase of the diameter of wafers to 300 mm makes them heavier to transport in lots. Automated Material Handling Systems (AMHS) are an excellent alternative to tackle this problem. Because of the high price of production equipment, the goal is to use production capacity as much as possible while avoiding to keep too much inventory. To reach this goal, it is important that the transportation and storage system ensures that machines do not wait for available lots, and also that lots do not wait for available machines. In the literature, due to the problem complexity (up to 700 steps, re-entrant flows, etc.), the modeling of transportation is made with strong assumptions on the production or vice-versa. However, transport is a service for production. This thesis aims at providing a modeling approach that allows the integration in details transport, production and storage constraints, in order to improve production key indicators. A detailed understanding of the system allows us to build of a discrete event simulation model which is, in our point of view, the best compromise between the necessary level of details and computational times. Finally, through industrial validations, the complete study of the model allows critical parameters of transport management to be analyzed. The results help to get a better understanding of the system and open interesting research perspectives.

Research in future generation computing is focused on reducing energy dissipation while maintaining the switching speed in a binary operation to continue the current trend of increasing transistor-density according to Moore’s law. Unlike charge-based CMOS technology, spin-based nanomagnetic technology, based on switching bistable magnetization of single domain shape-anisotropic nanomagnets, has the potential to achieve ultralow energy dissipation due to the fact that no charge motion is directly involved in switching. However, switching of magnetization has not been any less dissipative than switching transistors because most magnet switching schemes involve generating a current to produce a magnetic field, or spin transfer torque or domain wall motion to switch magnetization. Current-induced switching invariably dissipates an exorbitant amount of energy in the switching circuit that nullifies any energy advantage that a magnet may have over a transistor. Magnetoelastic switching (switching the magnetization of a magnetostrictive magnet with voltage generated stress) is an unusual switching paradigm where the dissipation turns out to be merely few hundred kT per switching event – several orders of magnitude less than that encountered in current-based switching. A fundamental obstacle, though, is to deterministically switch the magnetization of a nanomagnet between two stable states that are mutually anti-parallel with stress alone. In this work, I have investigated ways to mitigate this problem. One popular approach to flip the magnetizations of a nanomagnet is to pass a spin polarized current through it that transfers spin angular moment from the current to the electrons in the magnet, thereby switching their spins and ultimately the magnet’s magnetization. This approach – known as spin transfer torque (STT) – is very dissipative because of the enormous current densities needed to switch magnets, We, therefore, devised a mixed mode technique to switch magnetization with a combination of STT and stress to gain both energy efficiency from stress and deterministic 180o switching from STT. This approach reduces the total energy dissipation by roughly one order of magnitude. We then extended this idea to find a way to deterministically flip magnetization with stress alone. Sequentially applying stresses along two skewed axes, a complete 180o switching can be achieved. These results have been verified with stochastic Landau-Lifshitz-Gilbert simulation in the presence of thermal noise. The 180o switching makes it possible to develop a genre of magneto-elastic memory where bits are written entirely with voltage generated stress with no current flow. They are extremely energy-efficient. In addition to memory devices, a universal NAND logic device has been proposed which satisfies all the essential characteristics of a Boolean logic gate. It is non-volatile unlike transistor based logic gates in the sense that that gate can process binary inputs and store the output (result) in the magnetization states of magnets, thereby doubling as both logic and memory. Such dual role elements can spawn non-traditional non-von-Neumann architectures without the processor and memory partition that reduces energy efficiency and introduces additional errors. A bit comparator is also designed, which happens to be all straintronic, yet reconfigurable. Moreover, a straintronic spin neuron is designed for neural computing architecture that dissipates orders of magnitude less energy than its CMOS based counterparts. Finally, an experiment has been performed to demonstrate a complete 180o switching of magnetization in a shape anisotropic magnetostrictive Co nanomagnet using voltage generated stress. The device is synthesized with nano-fabrication techniques namely electron beam lithography, electron beam evaporation, and lift off. The experimental results vindicate our proposal of applying sequential stress along two skewed axes to reverse magnetization with stress and therefore, provide a firm footing to magneto-elastic memory technology.

Solar energy as the most abundant source of energy is clean, non-pollutant, and completely renewable, which provides energy security, independence, and reliability. Organic-inorganic hybrid perovskite solar cells (PSCs) revolutionized the photovoltaics field not only by showing high efficiency of above 22% in just a few years but also by providing cheap and facile fabrication methods. In this dissertation, fabrication of PSCs in both ambient air conditions and environmentally controlled N2-filled glove-box are studied. Several characterization methods such as SEM, XRD, EDS, Profilometry, four-point probe measurement, EQE, and current-voltage measurements were employed to examine the quality of thin films and the performance of the PSCs. A few issues with the use of equipment for the fabrication of thin films are addressed, and the solutions are provided. It is suggested to fabricate PSCs in ambient air conditions entirely, to reduce the production cost. So, in this part, the preparation of the solutions, the fabrication of thin films, and the storage of materials were performed in ambient air conditions regardless of their humidity sensitivity. Thus, for the first part, the fabrication of PSCs in ambient air conditions with relative humidity above ~36% with and without moisture sensitive material, i.e., Li-TFSI are provided. Perovskite materials including MAPbI3 and mixed cation MAyFA(1-y)PbIxBr(1-x) compositions are investigated. Many solution-process parameters such as the spin-coating speed for deposition of the hole transporting layer (HTL), preparation of the HTL solution, impact of air and light on the HTL conductivity, and the effect of repetitive measurement of PSCs are investigated. The results show that the higher spin speed of PbI2 is critical for high-quality PbI2 film formation. The author also found that exposure of samples to air and light are both crucial for fabrication of solar cells with larger current density and better fill factor. The aging characteristics of the PSCs in air and vacuum environments are also investigated. Each performance parameter of air-stored samples shows a drastic change compared with that of the vacuum-stored samples, and both moisture and oxygen in air are found to influence the PSCs performances. These results are essential towards the fabrication of low-cost, high-efficiency PSCs in ambient air conditions. In the second part, the research is focused on the fabrication of high-efficiency PSCs using the glove-box. Both single-step and two-step spin-coating methods with perovskite precursors such as MAyFA(1-y)PbIxBr(1-x) and Cesium-doped mixed cation perovskite with a final formula of Cs0.07MA0.1581FA0.7719Pb1I2.49Br0.51 were considered. The effect of several materials and process parameters on the performance of PSCs are investigated. A new solution which consists of titanium dioxide (TiO2), hydrochloric acid (HCl), and anhydrous ethanol is introduced and optimized for fabrication of quick, pinhole-free, and efficient hole-blocking layer using the spin-coating method. Highly reproducible PSCs with an average power conversion efficiency (PCE) of 15.4% are fabricated using this solution by spin-coating method compared to the conventional solution utilizing both spin-coating with an average PCE of 10.6% and spray pyrolysis with an average PCE of 13.78%. Moreover, a thin layer of silver is introduced as an interlayer between the HTL and the back contact. Interestingly, it improved the current density and, finally the PCEs of devices by improving the adhesion of the back electrode onto the organic HTL and increasing the light reflection in the PSC. Finally, a highly reproducible fabrication procedure for cesium-doped PSCs using the anti-solvent method with an average PCE of 16.5%, and a maximum PCE of ~17.5% is provided.

Electron Beam Induced Deposition (EBID) is a direct write fabrication process with applications in circuit edit and debug, mask repair, and rapid prototyping. However, it suffers from significant drawbacks, most notably low purity. Work over the last several years has demonstrated that deposition from bulk liquid precursors, rather than organometallic gaseous precursors, results in high purity deposits of low resistivity (LPEBID). In this work, it is shown that the deposits resulting from LP-EBID are only highly conductive when deposited at line doses below 25μC/cm. When the dose exceeds this value, the resulting structure is highly porous providing a poor conductive pathway. It is also shown that beam current has no significant effect on the resistivity of the deposits. Nanowires with resistivity significantly lower than the previous best result of 67μΩ•cm were achieved, with the lowest resistivity being only 6.6μΩ•cm, only a factor of 4 higher than that bulk copper of 1.7μΩ•cm.