No description available.

Fabrication of ordered anodic alumina nanopore arrays and anodization parameters including electrolyte, concentration, voltage, temperature and time have been investigated. Cobalt nanoparticles were electrodeposited at the bottom of the pores. Vertically aligned, open-tipped multi-walled carbon nanotube arrays of high density and uniformity were synthesized via a flame method on silicon substrates using a nanoporous template of anodized aluminum oxide. The diameter and length of the nanotubes are controlled by the geometry of the aluminum oxide template. It is the cobalt catalyst particles, not the porous aluminum templates, help the growth of carbon nanotubes through graphitization and bonding of carbon nanotubes to the silicon substrates. Fabrication of nano-structures has been demonstrated. Nano-trenches of 20 nm have been achieved using single-walled nanotube bundles as shadow masks, which were aligned across electrodes under high frequency AC voltage.

This work aims to study the pressure dependence of the thickness of the epitaxial silicon carbide SiC film growing from crystalline silicon Si due to the heterogeneous reaction with gaseous carbon monoxide CO.

No description available.

La substitution du canal de silicium par un semi-conducteur III-V est une des voies envisagées pour accroitre la mobilité des électrons dans les transistors n-MOSFET et ainsi réduire la consommation des circuits. Afin de réduire les coûts et de profiter des plateformes industrielles de la microélectronique, les transistors III-V doivent être réalisés sur des substrats de silicium. Cependant, la différence de paramètre de maille entre le Si et les couches III-V induit de nombreux défauts cristallins dans le canal du transistor, diminuant la mobilité des porteurs. L’objectif de cette thèse est la réalisation de transistors à canal III-V sur substrat de silicium au sein de la plateforme microélectronique du CEA Leti. Dans le cadre de ces travaux, deux filières technologiques d’intégration ont été développées pour la réalisation de transistors tri-gate à base d’In0,53Ga0,47As sur substrat de silicium : par un collage moléculaire d’une couche d’InGaAs sur InP et par une épitaxie directe de la couche d’InGaAs sur substrat Si. Les différentes étapes technologiques spécifiques à l’InGaAs ont été mises au point au cours de ces travaux, en prenant en compte les contraintes de contamination des équipements. Le traitement de surface de l’InGaAs et le dépôt du diélectrique de grille à haute permittivité (type high-k) par ALD ont été particulièrement étudiés afin de réduire la quantité d’états d’interface (Dit) et d’optimiser l’EOT. Pour cela, des analyses XPS et des mesures électriques C(V) de capacités MOS ont été réalisées à l’échelle d’un substrat de 300mm de diamètre. / The replacement of the silicon channel by III-V materials is investigated to increase the electron mobility in the channel and reduce the power consumption. In order to decrease the cost and to take advantage of the microelectronic silicon platform, III-V transistors must be built on Silicon substrates. However, the lattice parameter mismatch between Silicon and the III-V layers leads to a high defects density in the channel and reduces the carrier mobility. This thesis aims to realize III-V transistors on silicon substrate in the CEA-Leti microelectronic clean room. In the frame of this PhD, two integration process are elaborated to realize In0,53Ga0,47As tri-gate transistors on silicon: the molecular bonding of an InGaAs layer grown on a InP substrate, and the direct epitaxy of InGaAs on a silicon substrate. The fabrication steps for InGaAs transistors were developed, taking into account the clean room contamination restriction. InGaAs surface treatment and high-permittivity dielectric deposition by ALD are studied in order to reduce the density of interface states (Dit) and to optimize the EOT. XPS analysis and C(V) measurement are performed at the scale of a 300mm Silicon substrate.

The present work has been focused on the growth of Group III-nitride epitaxial layers and nanostructures on Si (111) substrates by plasma-assisted molecular beam epitaxy. Silicon is regarded as a promising substrate for III-nitrides, since it is available in large quantity, at low cost and compatible to microelectronics device processing. However, three-dimensional island growth is unavoidable for the direct growth of GaN on Si (111) because of the extreme lattice and thermal expansion coefficient mismatch. To overcome these difficulties, by introducing β-Si3N4 buffer layer, the yellow luminescence free GaN can be grow on Si (111) substrate. The overall research work carried out in the present study comprises of five main parts. In the first part, high quality, crack free and smooth surface of GaN and InN epilayers were grown on Si(111) substrate using the substrate nitridation process. Crystalline quality and surface roughness of the GaN and InN layers are extremely sensitive to nitridation conditions such as nitridation temperature and time. Raman and PL studies indicate that the GaN film obtained by the nitridation sequences has less tensile stress and optically good. The optical band gaps of InN are obtained between ~0.73 to 0.78 eV and the blueshift of absorption edge can be induced by background electron concentration. The higher electron concentration brings in the larger blueshift, due to a possible Burstein–Moss effect. InN epilayers were also grown on GaN/Si(111) substrate by varying the growth parameters such as indium flux, substrate temperature and RF power. In the second part, InGaN/Si, GaN/Si3N4/n-Si and InN/Si3N4/n-Si heterostructures were fabricated and temperature dependent electrical transport behaviors were studied. Current density-voltage plots (J-V-T) of InGaN/Si heterostructure revealed that the ideality factor and Schottky barrier height are temperature dependent and the incorrect values of the Richardson’s constant produced, suggests an inhomogeneous barrier at the heterostructure interface. The higher value of the ideality factor compared to the ideal value and its temperature dependence suggest that the current transport is primarily dominated by thermionic field emission rather than thermionic emission. The valence band offset of GaN/β-Si3N4/Si and InGaN/Si heterojunctions were determined by X-ray photoemission spectroscopy. InN QDs on Si(111) substrate by droplet epitaxy and S-K growth method were grown in the third part. Single-crystalline structure of InN QDs (droplet epitaxy) was verified by TEM and the chemical bonding configurations of InN QDs were examined by XPS. The interdigitated electrode pattern was created and (I-V) characteristics of InN QDs were studied in a metal–semiconductor–metal configuration in the temperature range of 80–300 K. The I-V characteristics of lateral grown InN QDs were explained by using the trap model. A systematic manipulation of the morphology, optical emission and structural properties of InN/Si (111) QDs (S-K method) is demonstrated by changing the growth kinetics parameters such as flux rate and growth time. The growth kinetics of the QDs has been studied through the scaling method and observed that the distribution of dot sizes, for samples grown under varying conditions, has followed the scaling function. In the fourth part, InN nanorods (NRs) were grown on Si(111) and current transport properties of NRs/Si heterojunctions were studied. The rapid rise and decay of infrared on/off characteristics of InN NRs/Si heterojunction indicate that the device is highly sensitive to the IR light. Self-aligned GaN nanodots were grown on semi-insulating Si(111) substrate. The interdigitated electrode pattern was created on nanodots using photolithography and dark as well as UV photocurrent were studied. Surface band gaps of InN QDs were estimated from scanning tunneling spectroscopy (STS) I-V curves in the last part. It is found that band gap is strongly dependent on the size of InN QDs. The observed size-dependent STS band gap energy blueshifts as the QD’s diameter or height was reduced.

Afin d’améliorer les performances électriques dans les circuits intégrés en 3D, une large modélisation électromagnétique et une caractérisation haute fréquence sont requises. Cela a pour but de quantifier et prédire les phénomènes de couplage par le substrat qui peuvent survenir dans ces circuits intégrés. Ces couplages sont principalement dus aux nombreuses interconnexions verticales par unité de volume qui traversent le silicium et que l’on nomme « Through Silicon Vias » (TSV).L’objectif de cette thèse est de proposer des règles d’optimisation des performances, à savoir la minimisation des effets de couplage par les substrats en RF. Pour cela, différentes configurations de structures de test utilisées pour analyser le couplage sont caractérisées.Les caractérisations sont effectuées sur un très large spectre de fréquence. Les paramètres d’analyse sont les épaisseurs du substrat, les architectures des vias traversant (diamètres, densités, types de barrières), ainsi que la nature des matériaux utilisés. Des modèles électriques permettant de prédire les phénomènes de couplage sont extraits. Différents outils pour l’analyse de ces effets, sont développés dans notre laboratoire. Parallèlement un important travail de modélisation 3D est mené de façon à confronter mesure et simulation et valider nos résultats. Des stratégies d’optimisation pour réduire ces phénomènes dans les circuits 3D ont été proposées, ce qui a permis de fournir de riches informations aux designers. / In order to improve the electrical performance in 3D integrated circuits, a large electromagnetic modeling and a high frequency characterization are required. This has for goal to quantifiy and predicts the substrate coupling phenomena that can occur in these integrated circuits. These couplings are mainly due to the numerous vertical interconnections existing in a small volume and passing through the silicon, and so called “Through Silicon Vias” (TSV). The objective of this thesis is to propose rules for electrical performance optimization, in order to minimize the coupling effects in RF substrates. For this reason, different test structures configurations used to analyze the coupling are characterized.The characterizations are performed on a very wide frequency spectrum. The analysis parameters are the thicknesses of the substrate, the TSV architectures (diameters, densities, types of barriers), and the nature of the used materials. Electrical models for predicting the coupling phenomena are extracted. Different tools for the analysis of these effects are developed in our laboratory. At the same time, a considerable amount of 3D modeling is conducted to compare measurements with simulations and validate our results. Optimization strategies to reduce coupling phenomena in 3D circuits have been proposed; this has provided a wealth of information to designers.

Cette thèse porte sur l’étude de la croissance auto-organisée de boîtes quantiques d’In(Ga)As sur substrat de silicium visant à l’intégration monolithique d’un émetteur de lumière sur silicium à base d’un matériau semiconducteur III-V. Le développement d’un tel système se heurte à deux verrous majeurs : le premier provient d’un très fort désaccord de maille qui rend difficile l’élaboration de boîtes quantiques d’In(Ga)As sur Si présentant de bonnes qualités structurales et optiques, et le second provient de la nature électronique de l’interface entre In(Ga)As et le Si dont il est prédit qu’elle est de type II et donc peu efficace pour l’émission de lumière. L’approche que nous avons proposée consiste à insérer des BQs d’In(Ga)As dans un puits quantique de silicium dans SiO2, fabriqué sur un substrat SOI. Les effets attendus de confinement quantique dans le puits de Si favoriseraient une interface In(Ga)As/Si de type I. D’un point de vue expérimental, nous avons donc étudié l’influence de différents paramètres de croissance (température de croissance, rapport V/III, quantité d’In(Ga)As déposé, teneur en indium des boîtes quantiques …) sur le mode de croissance et sur les propriétés structurales et optiques des BQs d’In(Ga)As épitaxiées sur substrat de Si(001). Nous avons proposé une interprétation des phénomènes microscopiques qui régissent la formation des boîtes quantiques d’In(Ga)As sur Si en fonction de la teneur en indium. Nous avons aussi montré qu’il est possible de fabriquer des boîtes quantiques d’In0,4Ga0,6As sur Si ne présentant pas de défauts structuraux liés à la relaxation plastique. La luminescence attendue des boîtes quantiques n’a pas pu être obtenue, probablement en raison de deux conditions requises mais antagonistes: la fabrication de boîtes quantiques de très haute qualité structurale (possible uniquement pour de l’In(Ga)As avec une teneur en In inférieure à 50%) et un alignement de bandes à l’interface BQs In(Ga)As/Si de type I (possible théoriquement pour une teneur en In supérieure ou égale à 70%). Ce travail a permis d’enrichir la connaissance et le savoir-faire concernant l’élaboration de boîtes quantiques d’In(Ga)As sur substrat de Si(001) et l’encapsulation de ces boîtes quantiques par du silicium dans un réacteur d’épitaxie par jets moléculaires III-V. / This thesis focuses on the study of the self-organized growth of In(Ga)As quantum dots (QDs) on a silicon substrate. The purpose of this work is to pave the way for a monolithic integration of III-V semiconductor-based light emitter on silicon. One of the big challenges of this project is to overcome the high lattice mismatch between InGaAs and Si which can induce structural defects in the QDs. Another key challenge comes from the expected type II In(Ga)As/Si interface that is detrimental for efficient light emission. In order to solve the “interface type” issue, we suggested to insert the In(Ga)As QD plane inside a thin silicon layer grown on a SOI substrate. Confinement effects of the Si/SiO2 quantum well are expected to raise the X-valley of the Si conduction band above the Γ-valley, leading to a type I interface in both direct and reciprocal space. The influence of different parameters (such as the amount of deposited In(Ga)As, the growth temperature, the V/III ratio and the gallium content...) on the growth mode and on the structural and optical properties of the In(Ga)As QDs grown on Si(001) are experimentally studied. We propose an interpretation of the microscopic phenomena governing the formation of the QDs as a function of gallium content. We finally show the possibility of making In0,4Ga0,6As QDs on Si(001) substrates, these QDs being free of ‘plastic relaxation’-related structural defects. The expected luminescence from the QDs was not obtained probably due to two incompatible conditions: the first, required for growing high structural quality QDs (possible only for In(Ga)As containing less than 50% of In) and the second, essential for maintaining a type I interface band alignment (theoretically possible for an In content greater than 50%). This work is contributing to the understanding of In(Ga)As QDs growth on Si(001) substrates and to the know-how of capping such QDs with silicon inside a III-V molecular beam epitaxy reactor.

No description available.

在二十一世紀中， LED發光二極體更是備受期待的節能產品。過去背光源一直是LED主要應用項目，而漸漸地照明也開始採用LED產品，甚至各國已宣布將禁用白熾燈。然而，在各國政府及業者大力推廣及投入LED產業之際，目前LED產品尚未能實現市場替代效應之事實卻不容忽視。細究其可能原因，是否LED產品仍有技術功能缺陷，抑或其價格無法競爭，又者消費者對產品認知不足、終端通路尚未成熟、品牌塑造尚待建立等因素，讓消費者暫時裹足不前? 鑒於台灣在LED產業中已有完整的上中下游布局，不但是下游封裝的全球最大供應中心，近年更也逐步紮根中游晶粒產品，甚至切入上游單晶基板、磊晶產品製程。故此，本研究希冀探查現有LED產品所遭遇之困難，以功能品質及經濟價值等角度，找尋可突破市場瓶頸之關鍵因素，並針對其中可進行專利檢索及分析的較具技術性因素：LED單晶基板，以中國大陸此成長最為顯著之市場作為專利檢索及分析之核心地理區域，探討LED單晶片基板之專利發展趨勢以及研發參考目標及方向。 在進行專利檢索之前，本研究將先行剖析現有LED單晶片基板的應有功能、重點特性、4大類基板材料選擇與其最新研發優勢，包含藍寶石、碳化矽、矽、氮化鎵，以助於後續專利檢索及分析結果之觀察思考。本研究的結論與建議將分別針對不同的LED單晶片基板材料選擇，以專利分析結果對照其市場發展近況，向台灣業者提出藍寶石、碳化矽已係過度競爭、不宜進入的項目，並在最後建議台灣業者仍可持續投入研發LED矽、氮化鎵基板材料，以及額外以技術與應用創新增加其產品的市場連結度及應用產業競爭利基。 / Nowadays LED has become a future mainstream of highly expected energy-saving product. Back-lighting has been the main application for LED, such as in monitors, and furthermore lighting has grown its market size into significance. However, it should draw attention that LED products has not yet fully replace conventional lighting as expected, due to a number of possible factors, including functions, prices, consumer awareness, channeling, and/or branding. In light of the fully established LED industry in Taiwan, including the largest downstream packaging supply source, mature middle-stream wafer production and leading upstream epitaxy and substrate manufacturing, this study aims to seek and find the patent searchable and analyzable part of the current LED obstacles in product quality and economic value perspective. As a result, single crystal substrate falls into abovementioned criteria, including four major substrate materials: sapphire, silicon carbonate, silicon, and gallium nitrite. This study further concentrates the patent search and analysis on China, the fastest growing LED market among all regions and the biggest opportunity for Taiwan players. Before patent search, this study gives a detailed elucidation about four substrate materials on functions, important traits, different types and respective R&D updates and breakthrough, followed by interpretation of and association with patent search and analysis. At the end of this study, conclusions and suggestions are given, based on Taiwan players’ current relative strength and weakness. In sum, sapphire substrates and silicon carbonate substrate have overly competitive patent and market situation, and silicon substrates and gallium nitrite substrate may allow Taiwan players to continue and/or reinforce R&D investment. Additionally, technology and application innovation could increase product-market linkage and competitive edge in LED application industry.