Esse trabalho consiste no estudo e desenvolvimento de técnicas de proteção a falhas transientes, também chamadas single event upset (SEU), em circuitos programáveis customizáveis por células SRAM. Os projetistas de circuitos eletrônicos estão cada vez mais predispostos a utilizar circuitos programáveis, conhecidos como Field Programmable Gate Array (FPGA), para aplicações espaciais devido a sua alta flexibilidade lógica, alto desempenho, baixo custo no desenvolvimento, rapidez na prototipação e principalmente pela reconfigurabilidade. Em particular, FPGAs customizados por SRAM são muito importantes para missões espaciais pois podem ser rapidamente reprogramados à distância quantas vezes for necessário. A técnica de proteção baseada em redundância tripla, conhecida como TMR, é comumente utilizada em circuitos integrados de aplicações específicas e pode também ser aplicada em circuitos programáveis como FPGAs. A técnica TMR foi testada no FPGA Virtex® da Xilinx em aplicações como contadores e micro-controladores. Falhas foram injetadas em todos as partes sensíveis da arquitetura e seus efeitos foram detalhadamente analisados. Os resultados de injeção de falhas e dos experimentos sob radiação em laboratório comprovaram a eficácia do TMR em proteger circuitos sintetizados em FPGAs customizados por SRAM. Todavia, essa técnica possui algumas limitações como aumento em área, uso de três vezes mais pinos de entrada e saída (E/S) e conseqüentemente, aumento na dissipação de potência. Com o objetivo de reduzir custos no TMR e melhorar a confiabilidade, uma técnica inovadora de tolerância a falhas para FPGAs customizados por SRAM foi desenvolvida para ser implementada em alto nível, sem modificações na arquitetura do componente. Essa técnica combina redundância espacial e temporal para reduzir custos e assegurar confiabilidade. Ela é baseada em duplicação com um circuito comparador e um bloco de detecção concorrente de falhas. Esta nova técnica proposta neste trabalho foi especificamente projetada para tratar o efeito de falhas transientes em blocos combinacionais e seqüenciais na arquitetura reconfigurável, reduzir o uso de pinos de E/S, área e dissipação de potência. A metodologia foi validada por injeção de falhas emuladas em uma placa de prototipação. O trabalho mostra uma comparação nos resultados de cobertura de falhas, área e desempenho entre as técnicas apresentadas. / This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

abstract: An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing. Spatial separation of critical nodes in the physical design of this approach mitigates multi-node charge collection (MNCC) upsets. An advanced encryption system implemented with the proposed design, compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation up to 18% over an improved version of the prior approach, with negligible area impact. It can save up to 2/3rd of the power consumption and reach maximum possible frequency, when used in non-redundant mode of operation. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2015

Cette thèse s'intéresse en premier lieu à l'analyse des effetsfonctionnels des erreurs dans laconfiguration de FPGAs à base de SRAM. Ces erreurs peuvent provenir deperturbations naturelles(rayonnements, particules) ou d'attaques volontaires, par exemple avecun laser. La famille Virtex IIde Xilinx est utilisée comme premier cas pratique d'expérimentation,puis une comparaison est réaliséeavec la famille AT40K de chez ATMEL. Ceci a permis de mieux comprendrel'impact réel dedifférentes sources de perturbations, et les motifs d'erreur devantréellement être pris en compte pouraméliorer la robustesse d'un circuit implanté sur ce type detechnologie. Cette étude a nécessité ledéveloppement d'outils de conception spécifiques, permettantd'automatiser les analyses. Uneméthodologie innovante est proposée pour l'évaluation de lasensibilité de la mémoire de configurationaux SEUs : une classification des bits de configuration est établie enfonction des effets produits parleur inversion sur le fonctionnement normal de l'application. Cecipermet de déterminer les zones lesplus critiques, autorisant le développement de stratégies deprotection sélectives et à faible coût. / This thesis deals primarily with the analysis of the functionaleffects of errors in the configuration ofSRAM-based FPGAs. These errors can be due either to naturalperturbations (radiations, particles) orto malicious attacks, for example with a laser. The Xilinx Virtex IIfamily is used as first case study,then a comparison is made with the ATMEL AT40K family. This workallowed us a betterunderstanding of the real impact of perturbations, and of the errorpatterns that need to be taken intoaccount when improving the robustness of a circuit implemented on thistype of technology. Thisstudy required the development of specific design tools to automatethe analyses. An innovativemethodology is proposed for the evaluation of the configuration memorysensitivity to SEUs: aclassification of configuration bits is made with respect to theeffects produced on the application by asingle bit-flip. This enables us to identify the most critical areas,and to propose selective hardeningsolutions, improving the global reliability of the application at low cost.

Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

A method for measuring system-on-a-chip (SoC) cache upsets is presented and evaluated. In contrast to methods that predict cache contents through analysis or memory access patterns, this method uses system registers to read cache memories directly, thereby creating and checking golden copies to detect individual memory upsets during operation. The test method is driven by the device under test itself and does not require a user to set or know a priori the cache contents. A bare-metal implementation of this “direct golden method” on a Zynq UltraScale+ MPSoC logged upsets in the device’s data cache, data tag, and TLB RAM memories during a neutron radiation beam test. For each of these memories, this direct golden method yields cache upset bit cross sections, such as 7.115 × 10^−16 cm^2 for the data cache. Confidence intervals for these bit cross sections overlap such intervals for three other methods, supporting this method’s validity and candidacy for future use.

Este trabalho consiste no estudo e análise da suscetibilidade a efeitos da radiação em projetos de circuitos gerados por ferramenta de Síntese de Alto Nível para FPGAs (Field Programmable Gate Array), ou seja, circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SOC). Através de um injetor de falhas por emulação usando o ICAP (Internal Configuration Access Port) localizado dentro do FPGA é possível injetar falhas simples ou acumuladas do tipo SEU (Single Event Upset), definidas como perturbações que podem afetar o funcionamento correto do dispositivo através da inversão de um bit por uma partícula carregada. SEU está dentro da classificação de SEEs (Single Event Effects), efeitos transitórios em tradução livre, podem ocorrer devido a penetração de partículas de alta energia do espaço e do sol (raios cósmicos e solares) na atmosfera da Terra que colidem com átomos de nitrogênio e oxigênio resultando na produção de partículas carregadas, na grande maioria nêutrons. Dentro deste contexto além de analisar a suscetibilidade de projetos gerados por ferramenta de Síntese de Alto Nível, torna-se relevante o estudo de técnicas de redundância como TMR (Triple Modular Redundance) para detecção, correção de erros e comparação com projetos desprotegidos verificando a confiabilidade. Os resultados mostram que no modo de injeção de falhas simples os projetos com redundância TMR demonstram ser efetivos. Na injeção de falhas acumuladas o projeto com múltiplos canais apresentou melhor confiabilidade do que o projeto desprotegido e com redundância de canal simples, tolerando um maior número de falhas antes de ter seu funcionamento comprometido. / This work consists of the study and analysis of the susceptibility to effects of radiation in circuits projects generated by High Level Synthesis tool for FPGAs Field Programmable Gate Array (FPGAs), that is, system-on-chip (SOC). Through an emulation fault injector using ICAP (Internal Configuration Access Port), located inside the FPGA, it is possible to inject single or accumulated failures of the type SEU (Single Event Upset), defined as disturbances that can affect the correct functioning of the device through the inversion of a bit by a charged particle. SEU is within the classification of SEEs (Single Event Effects), can occur due to the penetration of high energy particles from space and from the sun (cosmic and solar rays) in the Earth's atmosphere that collide with atoms of nitrogen and oxygen resulting in the production of charged particles, most of them neutrons. In this context, in addition to analyzing the susceptibility of projects generated by a High Level Synthesis tool, it becomes relevant to study redundancy techniques such as TMR (Triple Modular Redundancy) for detection, correction of errors and comparison with unprotected projects verifying the reliability. The results show that in the simple fault injection mode TMR redundant projects prove to be effective. In the case of accumulated fault injection, the multichannel design presented better reliability than the unprotected design and with single channel redundancy, tolerating a greater number of failures before its operation was compromised.

Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e células de memória 6T SRAM feitas com estes dispositivos. Para conseguir isso, foram usadas ferramentas TCAD para simular falhas transientes devido a impacto de íons pesados a nível dispositivo e nível circuito. As simulações neste ambiente tem como vantagem a simulação dos fatos e mecanismos que produz as falhas transientes e seus efeitos nos dispositivos, além de também servir para projetar virtualmente estes dispositivos e caraterizar eles para estas simulações. Neste caso, foram projetados três dispositivos para simulação: um transistor NMOS de 32nm Bulk, um transistor NMOS de 28nm FDSOI e um transistor NMOS de 28nm FDSOI High-K para fazer comparações entre eles. Estes dispositivos foram projetados, caraterizados e testados contra o impacto de íons pesados a níveis dispositivo e circuito. Como resultado obtido, transistor Bulk de 32nm teve, no pior caso, uma carga coletada de 7.57 e 7.19 vezes maior que a carga coletada pelo dispositivo FDSOI de 28nm e FDSOI High-K de 28nm respectivamente atingido pelo mesmo íon pesado de 100MeV-cm2/mg. Com estes dados foi possível modelar o comportamento da carga coletada de ambos dispositivos usando este íon pesado, atingindo os terminais de Fonte e Dreno em distintos lugares e ângulos. Usando a mesma ferramenta e os dados obtidos de carga coletada pelos testes anteriores, foram projetadas células de memória SRAM de 6 transistores. Isso foi para testar elas contra os efeitos do impacto de íons pesados nos transistores NMOS de armazenagem da dados. Neste caso, a Transferência Linear de Energia (LET) do íon necessária para fazer que o dado armazenado na SRAM Bulk mude é 12.8 vezes maior que no caso da SRAM FDSOI e 10 maior no caso da SRAM FDSOI High-K, embora a quantidade de carga coletada necessária para que o dado mude em ambas células seja quase a mesma. Com estes dados foi possível modelar os efeitos dos íons pesados em ambos circuitos, descobrir a Carga Crítica destes e qual é o mínimo LET necessário para que o dado armazenado nestas SRAMs mude. / This work shows a comparison of faults due to Single-Event Effects in 28nm Fully Depleted SOI (FDSOI), 28nm FDSOI High-K and 32nm Bulk CMOS devices, and in 6T SRAM memory cells made with these devices. To provide this, was used TCAD tools to simulate transient faults due to heavy ion impacts on device and circuit levels. The simulations in that environment have the advantage to simulate the facts and mechanisms which produce the transient faults and this effects on the electronic devices, it also allow to simulate the virtual device fabrication and to characterize them. In this case, two devices were created for the simulations: a 32nm Bulk NMOS transistor and a 28nm FDSOI NMOS transistor for compare them. These devices were created, characterized and tested against heavy ion impacts at device and circuit levels. The results show that 32nm Bulk transistor has, in the worst case, a collected charge 7.57 and 7.19 times greater than the 28nm FDSOI and 28nm FDSOI High-K respectively collected charge with the same 100MeV-cm2/mg heavy ion. With these data it was possible to model the behavior of the collected charge in both devices with the same heavy-ion, reach the Source and Drain Terminal in different places and angles. Using the same tools and the obtained collected charge data of previous simulations, it was designed 6 transistors SRAM Memory Cells. That is done to test these circuits against the heavy ion effects on the data-storage NMOS transistor. In this case, the necessary Ion Linear Energy Transfer (LET) to flip the Bulk SRAM is 12.8 greater than the FDSOI SRAM and 10 times greater than the FDSOI High- K SRAM case, although the amount of charge to flip the cells is almost the same in both cases. With these data it was possible to model the heavy-ion effects in both circuits, discover the Critical Charge of them and the minimum LET to flips these SRAMs.

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates reduced-precision redundancy (RPR) as an effective and efficient alternative to the popular triple modular redundancy (TMR) for FPGA-based communications systems. Fault injection experiments show that RPR can improve the failure rate of a communications system by over 20 times over the unmitigated system at a cost less than half that of TMR by focusing on the critical SEUs. This dissertation contrasts the cost and performance of three different variations of RPR, one of which is a novel variation developed here, and concludes that the variation referred to as "Threshold RPR" is superior to the others for FPGA systems. Finally, this dissertation presents several methods for applying Threshold RPR to a system with the goal of reducing mitigation cost and increasing the system performance in the presence of SEUs. Additional fault injection experiments show that optimizing the application of RPR can result in a decrease in critical SEUs by as much 65% at no additional hardware cost.