Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set.

No description available.

Consumer demands are driving the current trend in the microelectronics industry to make electronic products that are miniature, fast, compact, high-density, reliable and low-cost. The use of surface mount devices (SMDs) has helped to decrease the size of electronic packages through the use of solder bump interconnections between the devices and the substrates/printed wiring boards (PWBs). Solder bumps act as not only mechanical, but also electrical interconnections between the device and the substrate/PWB. Common manufacturing defects ¨C such as open, cracked, missing, and misaligned solder bumps ¨C are difficult to detect because solder bumps are hidden between the device and the substrate/PWB after assembly. The reliability of packaged electronic devices in storage and usage is a major concern in the microelectronics industry. Therefore, quality inspection of solder bumps has become a critical process in the microelectronics industry to help ensure product quality and reliability. In this thesis, a methodology for quality evaluation and reliability study of solder bumps in electronic packages has been developed using the non-destructive and non-contact laser ultrasound-interferometric technique, finite element and statistical methods in this research work. This methodology includes the following aspects: 1) inspection pattern ¨C specific inspection patterns are created according to inspection purpose and package formats, 2) laser pulse energy density calibration ¨C specific laser pulse power and excitation laser spot size are selected in terms of package formats, 3) processing and analysis methods, including integrated analytical, finite element and experimental modal analyses approach, advanced signal processing methods and statistical analysis method, 4) approach combining modal analysis and advanced signal processing to improve measurement sensitivity of laser ultrasound-interferometric inspection technique, and 5) calibration curve using energy based simulation method and laser ultrasound inspection technique to predict thermomechanical reliability of solder bumps in electronic packages. Because of the successful completion of the research objectives, the system has been used to evaluate a broad range of solder bump defects in a variety of packaged electronic devices. The development of this system will help tremendously to improve the quality and reliability of electronic packages.

Thesis (Ph. D.)--State University of New York at Binghamton, Mechanical Engineering Department, 2005. / Includes bibliographical references (leaves 149-155).

Thesis (M.S.)--State University of New York at Binghamton, Department of Systems Science & Industrial Engineering, 2005. / Includes bibliographical references.

The project contains theoretical research of electrotechnical manufacture for lead-free reflow soldering. It contains characterization of soldering processes. Includes variations of solder paste printing, principles of part placing and also reflow soldering process. The project appoints possibilities of testing solder joints strength, mainly focused on mechanical vibrations. It describes a design and preparation of solder joint strength test methods by mechanical vibrations. It compares influence of vibrations on part types and solder alloys.

The Master thesis deals with technology of mounting QFN packages on to the printed circuits boards. Describes also influence of shape and size of soldering pads and the amount of soldering paste with respect to the quality and the reliability. In first part overview of existing packages is summarised. Second part describes design of testing board and the factors which leads to eliminating errors during manufacturing process.

Sn/Pb solders are widely used by the electronics industry to provide both mechanical and electrical interconnections between electronic components and printed circuit boards. Solders with enhanced mechanical properties are required for high reliability for Surface Mount Technology (SMT) applications. One approach to improve the mechanical properties of solder is to add metallic or intermetallic particles to eutectic 63Sn/37Pb solder to form composite solders. Cu6Sn5 and Cu3Sn form and grow at the solder/copper substrate interface. The formation and growth of these intermetallics have been proposed as controlling mechanisms for solderability and reliability of solder/copper joints. The goal of this study was to investigate the diffusion kinetics and microstructures of six types of composite solder/copper joints.

The Sn/Pb eutectic alloy system is the most widely used joining material in the electronics industry. In this application, the solder acts as both an electrical and mechanical connection within and among the different packaging levels in an electronic device. Recent advances in packaging technologies, however, driven by the desire for miniaturization and increased circuit speed, result in severe operating conditions for the solder connection. In an effort to improve its mechanical integrity, metallic or intermetallic particles have been added to eutectic Sn/Pb solder, and termed composite solders. It was the goal of this study to investigate the growth and morphology of the two intermetallic phases (Cu6Sn5 and Cu3Sn) that form between a Cu substrate and Sn/Pb solder under different aging and annealing conditions.

Currently, there are two major driving forces for considering alternative materials to lead- based products, specifically interconnections, in electronics applications, including the impending legislation or regulations which may tax, restrict, or eliminate the use of lead and the trend toward advanced interconnection technology, which may challenge the limits of present soldering technology. The reliability of solder joints is a concern because fracture failures in solder joints accounts for 70% of failures in electronic components. Lead-free solders are being investigated as replacements for lead solders currently used in electronics. Thermo-mechanical properties describe the stresses accumulated due to thermal fatigue as a result of CTE mismatch within the system. By understanding the failure mechanisms related to lead-free solders, the application of lead- free solders could be more strategically designed for specific applications. The objective of this thesis is to observe microstructural change in large-area solder joints caused by thermal cycling and relate these changes to reliability issues in large-area lead and lead-free solder constructed semiconductor power devices. This study focused on the microstructural changes within the solder alloy of a large-area solder joint under thermal cycling conditions. Two major primary observations were made from this research, they are: 1) due to a combination of testing conditions and material properties, the lead-free solders, Sn/3.5Ag and Sn/Ag/0.7Cu, sustained the most severe damage as compared to Sn/37Pb, and 2) due to elevated stresses at the solder/substrate interface in a simulated power semiconductor device sample damage was found to be most severe. / Master of Science