L'acoblament de soroll a través del substrat en circuits integrats mixtos és un important problema que sovint limita les prestacions de la circuiteria analògica. Les característiques d'aquest tipus d'acoblament i els factors que en determinen la importància no són ben compresos, així que calen criteris per tal de triar les millor accions per a resoldre el problema. En els darrers anys s'han proposat algunes tècniques per reduir el soroll de substrat, tot i que no hi ha una idea clara de l'abast de la seva validesa, i de les condicions que calen per a la seva eficàcia. La majoria de l'esforç de recerca que s'ha dedicat a aquest tema s'ha centrat en el desenvolupament de models, que permetin la incorporació del substrat en les eines CAD que s'utilitzen en les fases de simulació dels dissenys. Per tant, aquests resultats de recerca no contribueixen a la comprensió dels aspectes rellevants de l'acoblament.En aquesta tesi doctoral s'ha realitzat un estudi analític i experimental que ha permès determinar les característiques tecnolòiques i de disseny que faciliten l'acoblament vers la circuiteria analògica. S'ha partit d'una caracterització de l'acoblament mitjançant un simulador de dispositius, on s'ha pogut comprovar la importància d'aspectes com el tipus de substrat, la velocitat de commutació dels dispositius, les seves dimensions, o el punt de polarització. La caracterització s'ha realitzat tant per tecnologies CMOS com BiCMOS, i ha estat completada amb mesures sobre estructures de test. Posteriorment s'ha portat a terme un anàlisi de la propagació del soroll en el substrat, amb el que s'han esbrinat les característiques tecnològiques i de polartizació que determinen l'atenuació del soroll. L'anàlisis'ha realizat suposant condicions de polarització ideals, i ha permès determinar el potencial d'algunes mesures per a la minimització de l'acoblament. A continuació s'ha fet una revisió de les diverses tècniques de modelació del substrat, i utilitzant algun dels models s'han pogut realitzar simulacions circuitals per a estudiar l'acoblament en circuits de dimensions realistes, tenint en compte factors com els elements paràsits dels terminals de l'encapsulat, la influència dels pads, o l'estratègia de polarització. Aquest estudi s'ha complementat amb el disseny d'un circuit mixte de test sobre el que s'han fet mesures per a verificar els resultats obtinguts, i corroborar els mecanismes que determinen l'acoblament. La tesi s'ha completat amb una revisió de l'eficàcia d'algunes tècniques específiques per a la reducció del soroll, i amb un estudi de l'evolució en tecnologies futures tant del soroll de commutació a les línies d'alimentació, com del soroll acoblat a través del substrat. / El acoplo de perturbaciones a través del sustrato de silicio en circuitos integrados mixtos representa un importante problema que a menudo limita las prestaciones de la circuiteria analógica. Hay una cierta incomprensión de las características del acoplo i de los factotres que que determinan su importancia, de forma que faltan criterios para implementar técnicas que reduzcan el problema. En los últimos años se han propuesto diversas técnicas para la reducción del ruido de sustrato, aunque no estan claros su rango de validez y las condiciones que se deben cumplir para su eficacia. La mayor parte del esfuerzo investigador realizado en este campo se ha centrado en el desarrollo de modelos que faciliten la incorporación del sustrato a las herramientas CAD utilizadas en la fase de simulación de un circuito. Por tanto, esta investigación no ofrece aportaciones en la comprensión de los aspectos relevantes del fenómeno.En esta tesis doctoral se ha realilzado un estudio analítico y experimental que ha permitido determinar las características tecnológicas y de diseño que facilitan el acoplo sobre la circuitería analógica. Se ha partido de una caracterización del acoplamiento mediante un simulador de dispositivos, donde se ha podido comprovar la importancia de aspectos como el tipo de sustrato, la velocidad de conmutación de los dispositivos, sus dimensiones, o el punto de polarización. La caracterización se ha realizado tanto para estructuras CMOS como BiCMOS, y ha sido completada con medidas sobre estructuras de test. Posteriomente se ha llevado a cabo un análisis de la propagación del ruido en el sustrato, con el que se han determinado las características tecnológicas y de polarización que determinan la atenuación del ruido. El análisis se ha realizado suponiendo condiciones de polarización ideales, y ha permitido determinar el potencial de algunas medidas para la minimización del acoplo. A continuación se ha realizado una revisión de las diversas técnicas de modelación del sustrato, y utilizando alguno de los modelos se han podido realizar simulaciones circuitales para estudiar el acoplo en circuitos de dimensiones realistas, teniendo en cuenta factores como los elementos parásitos de los terminales del encapsulado, la influencia de los pads, o la estrategia de polarización. Este estudio se ha complementado con el diseño de un circuito mixto de test sobre el que se han hecho medidas para verificar los resultados obtenidos, y corroborar los mecanismos que determinan el acoplo. La tesi se ha completado con una revisión de la eficacia de algunas técnicas específicas para la reducción del ruido, y con un estudio de la evolución en tecnologías futuras tanto del ruido de conmutación a través de las líneas de alimentación, como del ruido acoplado a través del sustrato. / Noise coupling through common silicon substrate in mixed-signal circuits is an important problem that often limits the performance of the analog circuitry. The characteristics of this type of coupling and the factors determining its importance are not well understood, so criteria to choose the best actions to solve the problem are needed. Several techniques to reduce substrate noise have been proposed in the last years, although there is no clear idea about their range of validity, and the conditions required for their efficacy. Most of the research effort done in this field has been centered on the development of models, in order to allow the incorporation of substrate in the CAD tools used in simulation design stages. Thus, these research results do not contribute to the understanding of the relevant aspects of coupling.In this thesis an analytic and experimental study has been done, which has allowed determining the technological and design characteristics relevant in the coupling. The study has started with a characterisation of coupling using a device simulator, which has allowed determining the importance of aspects such as substrate type, device switching speed, device dimensions, or their biasing. Characterisation has been done both for CMOS and BiCMOS technologies, and it has been completed with measurements on test structures. Next an analysis of noise propagation through the substrate has been carried out, which has allowed to find out the biasing and technological characteristics that determine noise attenuation. The analysis has been done assuming ideal biasing conditions, and the potentiality of some noise minimisation measures could be determined. Next a review of the different substrate modelling techniques has been done, and some of the models have been used to perform circuit simulations to study coupling in circuits of some complexity, taking into account factors such as package pins parasitics, the influence of the ring of pads, or the biasing strategy. This study has been complemented with the design and measurements of a mixed-signal test circuit, which allowed verification of the results previously obtained, and the coupling mechanism. Finally the thesis is completed with a review of the efficacy of noise-reducing specific techniques, and with the study of the trends of switching noise on power supply lines and substrate for near future technologies.

Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 87-92). Also available on the World Wide Web.

No description available.

<p>Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.</p><p>In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.</p><p>In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.</p> / Report code: LiU-Tek-Lic-2005:33.

This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts is compared both qualitatively and quantitatively with simulations. The difference between the N-P and P-P coupling is in the cross-coupling parameter. A new N-P model, which requires only five parameters, is proposed by taking advantage of an existing P-P model combined with the concept of a virtual separation. This model has been validated up to 2GHz with Medici simulations. The virtual separation concept has been validated with 2D/3D simulations and measurements from test structures fabricated in a 0.35μm TSMC CMOS heavily doped process. This model is useful when transistor switching noise is the dominant source of substrate noise. Applications of the new N-P model are demonstrated with circuit simulations. / Graduation date: 2004

Previous work at Stanford University has demonstrated that inductance in the substrate connection is the principal problem underlying the coupling of digital switching noise into analog circuits. The low impedance substrate can be treated as a single node over a local area. Switching in the digital circuits produces current transients in the substrate. These transients are subsequently amplified in the analog portions of the overall mixed-mode circuit. Various guard rings and other techniques, including the use of new logic circuit families, have been proposed to suppress this noise. This work demonstrates that by using the capacitance of a forward biased guard ring(s), the substrate noise at a specific frequency(ies) can be reduced by resonating the guard ring capacitance with the substrate lead inductance to provide a very low substrate-to-ground impedance. In this manner, noise at particular frequencies, which are problematic to the analog circuit, can be suppressed. Tuning can be accomplished by varying the current in the forward-biased guard ring diodes. / Graduation date: 1995

In order to assess and optimize layout strategies for minimizing substrate noise, it is necessary to have fast and accurate techniques for computing contact coupling resistances associated with the substrate. In this talk, we describe an extraction method capable of full-chip analysis which combines modest geometric approximations, a novel integral formulation, and an FFT-accelerated preconditioned iterative method. / Singapore-MIT Alliance (SMA)

In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate. Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers. The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended. A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations. / Articles I, II, III, IV, VII and IX are published with permisson from IEEE dated 07/05/18. Copyright IEEE.

<p>In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all</p><p>because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits</p><p>along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system.</p><p>The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency.</p><p>The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is</p><p>implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip.</p>

In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system. The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency. The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip.