In many digital signal processing applications, we often need some special function units that can compute complicated arithmetic functions such as reciprocal, logarithm, power of 2, trigonometric functions, etc. The most popular designs are based on look-up tables with polynomial approximation. However, the table size will increase significantly in accordance with precision. In this thesis, we propose a method called remapping to reduce the table size by using non-uniform segmentation. When we obtain the coefficients for all segments, we do not store them in order. By sorting the coefficients in the ROM ,we design a efficient hardware mapping. The method can reduce the ROM size with lower extra cost spent in address mapping for non-uniform segmentation.

In the field of automatic control, using a microprocessor application system to monitor and control an automatic system is quite common and its usage rate are still increasing. Microprocessor can support complex processes scheduling, and accurately control on time and position. However, even a highly professional programmer still needs a lot of time to maintain the control programs running on this kind of control system. The advent of the programmable logic controller (PLC), which consists of CPU, data memory, digital and analog I/O port, and power module provides an alternative for designing an automatic system. It¡¦s used in the field of industrial control widely. Compared to the microprocessor-based control systems, the PLC-based control systems have the advantage of providing a development environment for easily programming and maintaining. However, the high cost, poor signal processing ability, and the restriction on the function of device are the major drawbacks of PLC. To solve the problems described above, this paper taking the advantages from the PLC-based microprocessor-based control systems proposes a PLC-like development environment for creating a microprocessor- based control system. To accomplish this goal, according to the object- oriented concept, this paper classified the device in a microprocessor into four categories, GPIO, ADC, Timer and Serial-com. And also provides an interface window for users to set and access device register. In addition, this paper provides a set of user customizable task module tools to easily establish a PLC-like based system. Then system developers can write a program via a simple event-table-driven way, and build up the operating procedures according to the approach of sequential multitasking. Our research result make the building of microprocessor-based system can be clearly divided in to three stages, microprocessor manufacturer, advance user, and generally user which not only makes the development of product easier and faster but also meets the time-to-market demands. In the future, some advanced technologies can be added into this automatic controller development tools to make it smarter and more automatic. For example, the environment can support the developed technology for multi-thread and multi-core microprocessor to analysis and establish Instruction trace, and adjust the load balancing automatically. Or it can integrate the graphical programming allows users to program simpler and more intuitive.

This thesis presents a novel algorithm called ant colony optimization with dual pheromone tables (ACODPT) for improving the quality of ant colony optimization (ACO). The proposed algorithm works by adding a so-called ¡§negative¡¨ pheromone table to ACO to avoid the problem of ACO easily falling into local optima. By using the ¡§negative¡¨ pheromone table to eliminate the most impossible path to search for the new solution, the probability of selecting the remaining paths is increased, and so is the quality. To evaluate the performance of the proposed algorithm, ACODPT is compared with several state-of-the-art algorithms in solving the clustering problem. The experimental results show that the proposed algorithm can eventually prevent ACO from falling into local optima in the early iterations, thus providing a better result than the other algorithms in many cases.

none

Hash tables (HTs) are used to implement various lookup schemes and they need to be efficient in terms of speed, space utilization, and power consumptions. For IP lookup, the hashing schemes are attractive due to their deterministic O(1) lookup performance and low power consumptions, in contrast to the TCAM and Trie based approaches. As the size of IP lookup table grows exponentially, scalable lookup performance is highly desirable. For next generation high-speed routers, this is a vital requirement when IP lookup remains in the critical data path and demands a predictable throughput. However, recently proposed hash schemes, like a Bloomier filter HT and a Fast HT (FHT) suffer from a number of flaws, including setup failures, update overheads, duplicate keys, and pointer overheads. In this dissertation, four novel hashing schemes and their architectures are proposed to address the above concerns by using pipelined Bloom filters and a Fingerprint filter which are designed for a memory-efficient approximate match. For IP lookups, two new hash schemes such as a Hierarchically Indexed Hash Table (HIHT) and Fingerprint-based Hash Table (FPHT) are introduced to achieve a a perfect match is assured without pointer overhead. Further, two hash mechanisms are also proposed to provide memory and power efficient lookup for packet processing applications. Among four proposed schemes, the HIHT and the FPHT schemes are evaluated for their performance and compared with TCAM and Trie based IP lookup schemes. Various sizes of IP lookup tables are considered to demonstrate scalability in terms of speed, memory use, and power consumptions. While an FPHT uses less memory than an HIHT, an FPHT-based IP lookup scheme reduces power consumption by a factor of 51 and requires 1.8 times memory compared to TCAM-based and trie-based IP lookup schemes, respectively. In dissertation, a multi-tiered packet classifier has been proposed that saves at most 3.2 times power compared to the existing parallel packet classifier. Intrinsic hashing schemes lack of high throughput, unlike partitioned Ternary Content Addressable Memory (TCAM)-based scheme that are capable of parallel lookups despite large power consumption. A hybrid CAM (HCAM) architecture has been introduced. Simulation results indicate HCAM to achieve the same throughput as contemporary schemes while it uses 2.8 times less memory and 3.6 times less power compared to the contemporary schemes.

In an attempt to slow the exhaustion of the Internet Protocol (IP) address space, Class-less Inter-Domain Routing (CIDR) was proposed and adopted. However, the decision to utilize CIDR also increases the size of the routing table, since it allows an arbitrary partitioning of the routing space. We propose a scheme to reduce the size of routing table in the CIDR context. Our approach utilizes a well-known and highly efficient heuristic to perform 2-level logic minimization in order to compress the routing table. By considering the IP routing table as a set of completely specified logic functions, we demonstrate that our technique can achieve about 25% reduction in the size of IP routing tables, while ensuring that our approach can handle routing table updates in real-time. The resulting routing table can be used with existing routers without needing any change in architecture. However, by realizing the IP routing table as proposed in this thesis, the implementation requires less complex hardware than Ternary CAM (TCAM) which are traditionally used to implement IP routing tables. The proposed architecture also reduces lookup latency by about 46%, hardware area by 9% and power consumed by 15% in contrast to a TCAM based implementation.

The rollers of run out table in Hot Strip Mill are operated with variable high rotational speed under a severe environment of high temperature and much cooling water around. And the table takes long space about 128 meters of length with over 330 rollers. The rollers of this area often break down, and it takes long to make urgent repair. So it costs about ten million NT dollars per year for mill shut-down. Although some improvements have been made before, the troubles still happens frequently. Then the temporary countermeasures of shortening the maintenance cycle and increasing the grease supply have been applied to prevent the break-down frequency from aggravation . But it wastes the cost and does not meet the environmental policy. This study analyzes many damage phenomena. Then it assumes that the 75% of roller running break-down is bearing damage resulting from bad lubrication condition and abnormal axial load. The cooling water which penetrates into bearing housing will result in grease emulsification and its consistency diluting. This certainly causes the bad lubrication condition and bearing rusting. In the meantime, if the floating function of roller bearing is inactive, the bearings will be operated under abnormal high axial load and without appropriate lubrication. Then the bearing will be damaged rapidly and must be repaired quickly. In order to improve bad lubrication and bearing rusting, this study modifies sealing arrangement and grease feeding circuit for bearing housing with the special functions of water obstruction, drainage and resistance to prevent water penetration. In addition, the overflow of grease will be collected to meet the environmental needs. Meanwhile, to look for better water resistance and mechanical stability for greasing, the study also discusses the relationship between consistency variation and thickening soap base after grease emulsification. During a three-month running of the new design , the water contents are stably under 1.5% which has greatly advanced. And the quantity of grease supply is under 10% of existing one. In order to improve the inactive floating function of roller bearings, this study not only analyzes the derivation of problems but also modifies the dimensional tolerance and adds cylindricity of geometric tolerance for the bore of bearing housing. This will ensure complete loose fit and shape accuracy to prevent the interference fit between the bore and bearing caused by manufacturing inaccuracy or other mistakes

A Peer-to-Peer system is a distributed system whose component nodes participate in similar roles. Every user node (the peer) can exchange and contribute its resources to another one in the system. Similar to the case that peers may dynamically join and leave the system, the data will also be inserted into and removed from the system dynamically. Given a certain range, a range query will find any data item whose value within the range. For example, a range query can find all the Beatle's works between 1961 and 1968 for us. However, once the range data is distributed over a P2P system through the hash function which has been used largely in many P2P systems, the continuity of the range data is not guaranteed to exist. Therefore, finding the scattered data whose value within a certain range costs much in a P2P system. The Distributed Segment Tree method (DST) preserves the local continuity of the range data at each node by using a segment tree and can break any given range into minimum number of node intervals whose union constitutes the whole requested range. The DST method works based on the Distributed Hash Table (DHT) logic; therefore, it can be applied in any DHT-based P2P system. However, data distribution of the DST method may cause overlapping. When searching a data range, the DST method sends more number of requests than what is really needed. Although the DST method designs the Downward Load Stripping Mechanism, the load on peers still may not be balanced. The main reason of these problems is that the DST method applies the DHT logic to the P2P systems. Therefore, in this thesis, we propose a method called Structured Segment Tree (SST) that does not use the DHT logic but embeds the structure of the segment tree into the P2P systems. In fact, the P2P network topology of an SST is the structure of a segment tree. Unlike a DST, an SST can fully reflect the properties of the original segment tree. Each peer in our proposed P2P system represents a node of a segment tree. Data intervals at the same level are continuous and will not overlap with each other. The union of data intervals at a level with full nodes is totally the whole data range which the P2P system can support. When searching a data range, the SST method sends as many number of requests as needed. In addition, we add sibling links to preserve the spatial locality and speed up the search efficiency. For the issue of load balance, our SST method also performs better than the DST method. From our simulation, we show that the SST method routes less number of peers to locate the requested range data than the DST method. We also show that the load based on our method is more balanced than that based on the DST method.

Rotary tables are generally regarded as the forth axis of machining tools. Traditionally, gear sets are used as reducers in the rotary tables. In order to improve the positioning accuracy, load and efficiency of rotary tables, a rotary table which applies the roller gear cam reducer is proposed. From the deduction of the theory, applications of roller gear cam reducers in the industries can be achieved. This thesis is focused on developing the procedure as follows: Firstly, the type of roller gear cam reducer and design parameters are identified. Secondly, the mechanical characteristics of the device are analyzed. Finally, a rotary table is designed and implemented to investigate the performance of the of the roller gear cam rotary table.

Recently, many industries pursue the goal of automatic high-speed assembly and manufacturing. So how to meet the requirement of high-precision and high-speed automatic assembly equipment is an important issue. In automatic assembly equipment, the high-speed indexing devices have been widely used because of their features of high precision, no backlash, and compactness. With increasing operating speeds, the problems of shortage of motor power, poor indexing accuracy, vibration, and noise shall be solved. The torque compensation mechanism that is to be developed here is applied to keep motors operating at constant speeds by compensating the required torque. In previous researches, the researchers all devote to study torque compensation based on synchronous time chart. In this paper, it is aimed at compensation of the time control chart according the point of view of energy and the system model is built to simulate dynamic response of the system. Through the results of simulation and experiment, we will discover the relations between the compensation time chart and parameters about the high-speed indexing devices. It is expected to improve the precision of indexing devices according to those effective compensation time control charts.