This thesis develops semi-automated methods to generate testbenches for VHDL models of communication systems. To illustrate the methods, a VHDL model was constructed for the speech-coding channel of the Global System for Mobile Communication (GSM). GSM is the Pan-European digital mobile telephony standard specified by the European Telecommunication Standards Institute (ETSI). This thesis emphasizes the error detection and error correction procedures that form an important part of the standard. First, a test bench template was generated using "Testbench Pro", a waveform generation tool developed by SynaptiCAD. The template includes a random sequence of speech data. A C program was then developed as a user interface to control the simulation procedure. Using the C program, the user can select a test bench template and specify the input test vectors. The C program adds the user's test vectors to the test bench template to create a final VHDL test bench that is ready for simulation. The testing data is then encoded by the GSM encoder models, passed through the noisy channel model that introduces errors into the data stream and, finally, passed through the GSM decoder models which attempt to correct the channel errors. Sophisticated error detection and error correction algorithms are used in the encoder/decoder models to increase the reliability of data transmission over the noisy channel. Finally, the original speech data is compared to the decoder output to detect any remaining bit errors and to evaluate the system performance. The simulation system is semi-automated. The user selects a set of parameters using the C program interface. A testbench is then automatically created and simulated. Two final report files are automatically generated. No user interaction is needed after the initial parameter selection. Several experiments were performed to illustrate the various features of the automated testbench generation system. / Master of Science

Made available in DSpace on 2014-06-12T15:58:18Z (GMT). No. of bitstreams: 2 arquivo3452_1.pdf: 3452194 bytes, checksum: f140ad60d48eddac72b254cec44bfe46 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2011 / O advento das novas tecnologias Very Large Scale Integration (VLSI) e o crescimento da demanda por produtos eletrônicos no mundo estão trazendo um aumento explosivo na complexidade dos circuitos eletrônicos. A contrario sensu, o tempo de mercado (time-tomarket) de um produto eletrônico, e o tempo de projeto necessário para produção e venda de um sistema estão ficando cada vez menores. Para que o circuito integrado chegue ao mercado com o funcionamento esperado é necessário realizar testes. Parte desses testes é chamada de verificação funcional e é a parte do projeto que requer mais tempo de desenvolvimento. Buscam-se sempre novos métodos que permitam que a verificação funcional seja realizada de forma ágil, fácil e que proveja uma maior reusabilidade e diminuição da complexidade na construção do ambiente de simulação, sem interferir negativamente na qualidade do processo de verificação e do produto. Dessa forma, o uso de uma metodologia de verificação funcional eficiente e de ferramentas que auxiliem o engenheiro de verificação funcional é de grande valia. A metodologia OVM_tpi permite o desenvolvimento de todo o fluxo de construção de um ambiente de verificação, independente da escolha feita pela equipe desenvolvedora, de forma que o ambiente de simulação seja gerado antes da implementação do circuito a ser verificado (Design Under Verification - DUV). Além disso, ataca os principais desafios do processo de verificação funcional, tempo e custo de desenvolvimento, contribuindo para uma diminuição da complexidade, reusabilidade, comunicação entre o ambiente com uma interface bem definida e diminuição no tempo de desenvolvimento de um testbench através do uso de templates que criam de forma semiautomática partes do ambiente de verificação. OVM_tpi teve como principal base a metodologia Open Verification Methodology (OVM), utilizando sua biblioteca para a construção do testbench e o paradigma de linguagem orientação objeto suportado por SystemVerilog, linguagem criada especialmente para verificação funcional e design. Sua validação foi através de estudos de casos que demonstraram a eficácia do seu uso, tanto para circuitos unidirecionais, quanto para bidirecionais

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En el ámbito del diseño de circuitos integrados, el proceso de asegurar que la intención del diseño es mapeada correctamente en su implementación se denomina verificación funcional. En este contexto, los errores lógicos son discrepancias entre el comportamiento previsto del dispositivo y su comportamiento observado. La verificación funcional es hoy en día el cuello de botella del flujo de diseño digital y la simulación de eventos discretos sigue siendo la técnica de verificación más utilizada, principalmente debido a que es la única aplicable a sistemas grandes y complejos. En este trabajo se aborda, mediante un enfoque teórico práctico, dos de los conceptos más relevantes de la verificación funcional de hardware basada en simulación, esto es, la arquitectura de los testbenches, los cuales le dan soporte práctico a dicha técnica y los modelos de cobertura funcional, los cuales definen las funcionalidades y escenarios que deben ser probados guiando de esta forma la creación de pruebas y el respectivo progreso del proceso de verificación. En primer lugar, se encara la temática de la arquitectura de los testbenches modernos identificando las propiedades deseadas de los mismos, reusabilidad y facilidad para aumentar el nivel de abstracción. En función de estas dos propiedades se selecciona la metodología de Universal Verification Methodology (UVM) para el diseño, análisis e implementación de dos testbenches. En segundo lugar, dada la problemática del crecimiento del espacio de prueba de los diseños modernos y la subsecuente dificultad para generar modelos de cobertura adecuados para los mismos a partir de sus especificaciones, se introduce un método empírico de caja negra para derivar un modelo de cobertura para diseños dominados por el control. Este método está basado en la utilización de un modelo abstracto de la funcionalidad del dispositivo bajo prueba (DUV, sigla en inglés de Device Under Verification). Este modelo facilita la extracción de conjuntos de secuencias de prueba, los cuales representan el modelo de cobertura funcional. Dada la complejidad de los posibles espacios de prueba generados, las conocidas técnicas de Testing de Software, partición en clases de equivalencia y análisis de valores límites, son aplicadas para reducirlos. Adicionalmente, se desarrolla una notación formal para expresar las secuencias de prueba equivalentes extraídas del modelo. Por ultimo se aplica el método de derivación de modelo de cobertura funcional presentado para obtener casos de prueba relevantes para un modulo de buffer FIFO, y se utiliza el testbench implementado para darle soporte a la ejecución de dichos casos de prueba, implementando las pruebas derivadas y los correspondientes puntos de cobertura, combinando de esta forma los dos conceptos abordados. / In the integrated circuit design field, the process of assuring that the design intent is properly mapped in its implementation is known as functional verification. In this context, logic errors are discrepancies between the device’s expected behavior and its observed behavior. The functional verification of a design is now a days the bottleneck of the digital design flow and discrete event simulation still is the most used verification technique, mostly because it is the only technique which is applicable to big and complex systems. In this work, through a theoretical and practical approach, two of the most relevant simulation based hardware functional verification concepts are addressed. Those concepts are, the testbench architecture, which gives practical support to the simulation technique, and the functional coverage model, which defines the functionalities and scenarios that should be tested, guiding the creation of tests and the measurement of the verification process’s progress. In first place, modern testbench architectures are studied identifying their desired properties, which are reusability and the facility to raise the level of abstraction. According to these properties the Universal Verification Methodology (UVM) is chosen for the design, analysis and implementation of two testbenches. In second place, given the test space growth challenge of modern designs and the subsequent difficulty for generating their appropriate coverage models from their specifications, an empirical black box method is introduced for the creation of coverage models for control dominated designs. This method is based in the definition of a functional model of the DUV (Design Under Verification) which facilitates the extraction of sets of test sequences which define a functional coverage model. Given the complexity of the test space, the well known software testing techniques, equivalence class partition and limit value analysis, are applied to reduce it. A formal notation is developed in order to express equivalent test sequences. Lastly, the presented functional coverage creation method is applied to a FIFO (First Input First Output) buffer module in order to obtain relevant test sequences, and one of the previously implemented testbench is used to give support to the execution of those test cases, implementing the test sequences and its corresponding coverage points, combining in this manner both of this work addressed concepts.

According to references, testing and verification of a hardware circuit project occupy about 60%˜70% of project time. Now that product cycle time is decreasing, verification methodology is an important parameter for effective and successful completion of a design project. Enhanced processor functions also make verification conditions more difficult. In this thesis the processor SYS32IME III, which is constructed based on architecture of ARM 1022E, is verified by using V5TE instruction set. This thesis focus on processor verification flow and others to help verification method. The verification language that is used to help generate testbench are described in this paper. Also, corner cases are generated, producing test cases that may be reused in different verification environments. Lastly, errors from CPU architecture, verification environments, interface wrapper and instruction set simulator were found in different verification environment and fixed. To conclude the study, insertion of self-implemented RTL monitor circuit into CPU architecture supply verification information about testbench¡¦s coverage of functional verification.

Verification and debug of integrated circuits for embedded applications has grown in importance as the complexity in function has increased dramatically over time. Various modeling and debugging techniques have been developed to overcome the overwhelming challenge. This thesis attempts to address verification and debug methods by presenting an accurate C model at the bit and algorithm level coupled with an implemented Hardware Description Language (HDL). Key concepts such as common signal and variable naming conventions are incorporated as well as a stepping function within the implemented HDL. Additionally, a common interface between low-level drivers and C models is presented for early firmware development and system debug. Finally, selfchecking verification is discussed for delivering multiple test cases along with testbench portability.

Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.

In todays fast evolving mobile communications the requirements of higher datarates are continuously increasing, pushing operators to upgrade the backhaul to support these speeds. A cost eective way of doing this is by using microwave links between base stations, but as the requirements of data rates increase, the capacity of the microwave links must be increased. This thesis was part of a funded research project with the objective of developing the next generation high speed microwave links for the E-band. In the research project there was a need for a testing system that was able to generate a series of test signals with selectable QAM modulations and adjustable properties to be able to measure and evaluate hardware within the research project. The developed system was designed in a digital domain using an FPGA platform from Altera, and had the ability of selecting several types of modulations and changing the properties of the output signals as requested. By using simulation in several steps and measurements of the complete system the functionality was verified and the system was delivered to the research project successfully. The developed system can be used to test several dierent modulators in other projects as well and is easily extended to provide further properties.

The purpose of this thesis work was to develop a Hardware-in-the-Loop imaging setup that enables experimenting with an event-based and frame-based camera under simulated space conditions. The generated data sets were used to compare visual navigation algorithms in terms of an event-based and frame-based feature detection and tracking algorithm. The comparative analyses of the feature detection and tracking algorithms were used to get insights into the feasibility of event-based vision near-space space objects. Event-based cameras differ from frame-based cameras by how they produce an asynchronous and independent stream of events caused by brightness changes at each pixel instead of capturing images at a fixed rate. The setup design is based on a theoretical framework incorporating optical calculations. These calculations indicating the asteroid model needed to be scaled down by a factor of 3192 to fit inside the camera depth-of-view. This resulted in a scaled Bennu asteroid with a size of 16.44 centimeters.The cameras under testing conducted three experiments to generate data sets. The utilization of a feature detection and tracking algorithm on both camera data sets revealed that the absolute number of tracked features, computation time, and robustness in various scenarios of the frame-based camera algorithm outperforms the event-based camera algorithm. However, when considering the percentages of tracked features relative to the total detected features, the event-based algorithm tracks a significantly higher percentage of features for at least one key frame than the frame-based algorithm.  The comparative analysis of the experiments performed in space-simulated conditions during this project showed that the feasibility of an event-based camera using solely events is low compared to the frame-based camera.

Detta examensarbete har utförts på uppdrag av Stegia AB. Stegias linjärmotorerprovas i en testbänk innan motorerna skickas till den slutliga kunden. Idag finns ettbehov av en testbänk som skall samla in data från utförda tester, minska risken atttesterna utförs fel, samt att testbänken skall vara lättare att använda för produktionspersonalen.Idag innehåller linjärmotortestet många manuella arbetsmoment,vilket innebär en hög risk för felaktiga resultat utan möjlighet till spårbarhet i testresultatet.Målet med detta arbete är att förenkla det slutliga testet av linjärmotorerför produktionspersonal, samt att minska risken för felaktigt utförda tester genomtestautomatisering. Resultatet presenteras i form av en prototyp som har konstruerats,vars syfte är att förbättra test av linjärmotorerna genom att uppfylla målet atträtt utförda tester görs på motorerna. Resultatet säkerställs genom validering ochutvärdering och analys av den framtagna prototypen. / This diploma work has been carried out on behalf of Stegia AB. Stegia manufacturesand sells linear motors that are tested in a test bench before shipped to thecustomer. Today there is a need for a test bench that collects test results from theperformed tests. The company would like to lower the risk of falsely made tests,and to make the test bench easier for the production staff to use. At this moment,the test of the linear motors is made up of several manual tasks before the test iscompleted. This increases the risk of wrong results because of incorrectly madetests, with no traceability of the results. The goal with this diploma work is to lowerthe risk of incorrect test result by automating the testing process for the productionstaff. The result is presented as a prototype, that should increase the reliability ofthe test result of the motors. The result is then validated and analyzed in this report.