Commercial off-the-shelf (COTS) microcontrollers can be useful for non-critical processing on spaceborne platforms. Many of these microprocessors are inexpensive and consume little power. However, the software running on these processors is vulnerable to radiation upsets, which can cause unpredictable program execution or corrupt data. Space missions cannot allow these errors to interrupt functionality or destroy gathered data. As a result, several techniques have been developed to reduce the effect of these upsets. Some proposed techniques involve altering the processor hardware, which is impossible for a COTS device. Alternately, the software running on the microcontroller can be modified to detect or correct data corruption. There have been several proposed approaches for software mitigation. Some take advantage of advanced architectural features, others modify software by hand, and still others focus their techniques on specific microarchitectures. However, these approaches do not consider the limited resources of microcontrollers and are difficult to use across multiple platforms. This thesis explores fully automated software-based mitigation to improve the reliability of microcontrollers and microcontroller software in a high radiation environment. Several difficulties associated with automating software protection in the compilation step are also discussed. Previous mitigation techniques are examined, resulting in the creation of COAST (COmpiler-Assisted Software fault Tolerance), a tool that automatically applies software protection techniques to user code. Hardened code has been verified by a fault injection campaign; the mean work to failure increased, on average, by 21.6x. When tested in a neutron beam, the neutron cross sections of programs decreased by an average of 23x, and the average mean work to failure increased by 5.7x.

This research investigates how ultrasonic damage monitoring in civil structures can be implemented on a small, battery-powered, self-contained device. The device is intended for the continuous monitoring of surface breaking cracks in steel using Rayleigh waves. This study in detail presents the challenges that are to be considered for the intended ultrasonic monitoring, with the objective to provide a foundation for the future development of a fully autonomously operating device. The study proposes a suitable hardware and software layout, and a prototype device is built using a digital signal processor, a commercial wireless transceiver, and custom amplification circuits. With the help of two narrowband ultrasonic contact transducers in a pitch-catch setup and appropriate contact wedges, the wave field that arises from scattering of an incident tone burst wave at a crack is measured. A data analysis algorithm extracts wave burst signals from the acquired output in order to minimize the data that is to be transmitted. Additional compression of the data and the implementation of a communication protocol allow for a reliable and efficient wireless transmission. In order to demonstrate the feasibility of the proposed approach, measurements of notches in a steel plate with different depths are taken. Measurement results from experiments with commercial ultrasonic equipment are compared to measurements taken with the prototype device. The influence of the sampling distortions on the signals are analyzed. The scope of this study is limited to a qualitative analysis of the experimental results; quantitative methods to determine the dimensions of a crack or notch from the measured data are not included. The research conducted demonstrates that taking ultrasonic measurements with a small, self-contained device is feasible. Comparison of frequency-based to time-based signal analysis methods yields that frequency-based methods are preferable, as they are affected less by sampling effects. The experimental results show that the intended ultrasonic examination technique can be used for qualitative damage assessment. The knowledge gained in this study contributes to improving the safety of civil infrastructure. Continuous local damage monitoring as proposed helps to detect critical conditions in-time, and to take countermeasures to avoid catastrophic failures.

This master’s thesis deals with rebuild of RC car model for use of autonomous sensors. Practical part of the thesis is divided to five main parts. The First part deals about selection of suitable RC model. Next part of thesis deals with detailed description of the RC model. The third part of thesis deals about selection of microcontroller which will be processing the model control. The fourth part of thesis deals about construction changes of the model. The last part of thesis deal about Simulink control of the vehicle.

This diploma thesis discusses the implementation of a GCC target for the Texas Instruments TMS320C6000 DSP platform. To this end, it makes use of mechanisms offered by GCC for porting to new target architectures. GCC internals such as the handling of conditional jumps and the layout of stack frames are investigated and applied to the new architecture. / Diese Diplomarbeit behandelt die Implementierung eines GCC-Targets für die DSP-Plattform TMS320C6000 von Texas Instruments. Dazu werden Mechanismen genutzt, die GCC für die Portierung auf neue Zielplattformen anbietet. GCC-Interna, wie die Behandlung bedingter Sprünge und das Layout von Stack-Frames, werden untersucht und auf die neue Architektur angewendet.

This diploma thesis discusses the applicability of GCC optimization algorithms for the TI TMS320C6x processor family. Conditional and Parallel Execution is used to speed up the resulting code. It describes the optimization framework of the GCC version 4.0 and the implementation details. / Diese Diplomarbeit behandelt die Anwendbarkeit der verschiedenen GCC Optimierungsalgorithmen für die TI TMS320C6x Prozessorfamilie. Bedingte und parallele Ausführbarkeit werden zur Beschleunigung eingesetzt. Sie beschreibt den Rahmen in dem die Optimierungen in Version 4.0 des GCC stattfinden und Details zur Implementierung.

This work deals with the design of universal wireless timer for fire sport disciplines. Fire sport is a group of more than 15 disciplines. There are different ways of time measurement for each discipline. Important part of this work is detailed research of individual disciplines and their requirements at time measurement system and it's accessories. Another part of this work deals with the specification of wireless timekeeping system, which involves suitable partitioning of time measurement system into wirelessly communication modules. The interface for connecting sensors and accessories is also specified. Designed system is suitable for racing and training purposes, it has short installation time. This work also deals with the design of electronics (power and digital circuits) for each module and also with building of prototype, which is tested using prepared scenarios. New findings are evaluated and lead to design of next generation of time measurement system.

This thesis deals with design and implementation of flexible modular electronic stopwatch system for use in resport. One of the advantages of the system is possibility of using wireless communication with sensors and displays. Developed system consist of main control unit, external display, wireless modules for communication with the sensors and desktop application that collects data and controls the system. Solution of system components, communication between them and method of time synchronization of wireless devices is also described in this thesis.

Diploma thesis is about narrowband PLC communication standards. The theoretical part describes details of all available OFDM standards including G3-PLC, PRIME, IEEE-1901.2 and G.hnem. The practical part deals with PRIME and G3-PLC standards. In this part is also compared OFDM technology with system of single carrier frequency in environment with real interferences. The last part describes developement of two firmwares for PLC modems Texas Instruments TMDSPLCKIT-V3, which allow UART communication and remote data collection. The thesis also includes Windows application developed to display and save collected data.

This project describes a concept of a library architecture that will enable to hide platform-specific behaviour of different MCUs under an united API that will enable the developers to develop portable applications. After a short summary of the current situation, the report describes the main principles of the library-to-be followed by definitions of behaviour of each module that can be controlled using the library. Then this report describes techniques used in the implementation and platform specifics. In the conclusion there is an idea of the direction in which the development could continue.

The energy consumption of large-scale high-performance computer (HPC) systems has become one of the foremost concerns of both data-center operators and computer manufacturers. This has renewed interest in alternative computer architectures that could offer substantially better energy-efficiency.Yet, the for the evaluation of the potential of these architectures necessary well-optimized implementations of typical HPC benchmarks are often not available for these for the HPC industry novel architectures. The in this work presented LU factorization benchmark implementation aims to provide such a high-quality tool for the HPC industry standard high-performance LINPACK benchmark (HPL) for the eight-core Texas Instruments TMS320C6678 digitalsignal processor (DSP). The presented implementation could perform the LU factorization at up to 30.9 GF/s at 1.25 GHz core clock frequency by using all the eight DSP cores of the System-on-Chip (SoC). This is 77% of the attainable peak double-precision floating-point performance of the DSP, a level of efficiency that is comparable to the efficiency expected on traditional x86-based processor architectures. A presented detailed performance analysis shows that this is largely due to the optimized implementation of the embedded generalized matrix-matrix multiplication (GEMM). For this operation, the on-chip direct memory access (DMA) engines were used to transfer the necessary data from the external DDR3 memory to the core-private and shared scratchpad memory. This allowed to overlap the data transfer with computations on the DSP cores. The computations were in turn optimized by using software pipeline techniques and were partly implemented in assembly language. With these optimization the performance of the matrix multiplication reached up to 95% of attainable peak performance. A detailed description of these two key optimization techniques and their application to the LU factorization is included. Using a specially instrumented Advantech TMDXEVM6678L evaluation module, described in detail in related work, allowed to measure the SoC’s energy efficiency of up to 2.92 GF/J while executing the presented benchmark. Results from the verification of the benchmark execution using standard HPL correctness checks and an uncertainty analysis of the experimentally gathered data are also presented. / Energiförbrukningen av storskaliga högpresterande datorsystem (HPC) har blivit ett av de främsta problemen för såväl ägare av dessa system som datortillverkare. Det har lett till ett förnyat intresse för alternativa datorarkitekturer som kan vara betydligt mer effektiva ur energiförbrukningssynpunkt. För detaljerade analyser av prestanda och energiförbrukning av dessa för HPC-industrin nya arkitekturer krävs väloptimerade implementationer av standard HPC-bänkmärkningsproblem. Syftet med detta examensarbete är att tillhandhålla ett sådant högkvalitativt verktyg i form av en implementation av ett bänkmärkesprogram för LU-faktorisering för den åttakärniga digitala signalprocessorn (DSP) TMS320C6678 från Texas Instruments. Bänkmärkningsproblemet är samma som för det inom HPC-industrin välkända bänkmärket “high-performance LINPACK” (HPL). Den här presenterade implementationen nådde upp till en prestanda av 30,9 GF/s vid 1,25 GHz klockfrekvens genom att samtidigt använda alla åtta kärnor i DSP:n. Detta motsvarar 77% av den teoretiskt uppnåbara prestandan, vilket är jämförbart med förväntningar på effektivteten av mer traditionella x86-baserade system. En detaljerad prestandaanalys visar att detta tillstor del uppnås genom den högoptimerade implementationen av den ingående matris-matris-multiplikationen. Användandet av specialiserade “direct memory access” (DMA) hårdvaruenheter för kopieringen av data mellan det externa DDR3 minnet och det interna kärn-privata och delade arbetsminnet tillät att överlappa dessa operationer med beräkningar. Optimerade mjukvaruimplementationer av dessa beräkningar, delvis utförda i maskinspåk, tillät att utföra matris-multiplikationen med upp till 95% av den teoretiskt nåbara prestandan. I rapporten ges en detaljerad beskrivning av dessa två nyckeltekniker. Energiförbrukningen vid exekvering av det implementerade bänkmärket kunde med hjälp av en för ändamålet anpassad Advantech TMDXEVM6678L evalueringsmodul bestämmas till maximalt 2,92 GF/J. Resultat från verifikationen av bänkmärkesimplementationen och en uppskattning av mätosäkerheten vid de experimentella mätningarna presenteras också.