A novel polymer semiconductor with side chains thermally cleavable at a low temperature of 200 °C was synthesized. The complete cleavage and removal of the insulating 2-octyldodecanoyl side chains were verified with TGA, FT-IR, and NMR data. The N-H groups on the native polymer backbone are expected to form intermolecular hydrogen bonds with the C=O groups on the neighboring polymer chains to establish 3-D charge transport networks. The resulting side chain-free conjugated polymer is proven to be an active p-type semiconductor material for organic thin film transistors (OTFTs), exhibiting hole mobility of up to 0.078 cm2V-1s-1. This thermo-cleavable polymer was blended with PDQT to form films that showed a higher performance than the pure individual polymers in OTFTs. MoO3 or NPB was used as a hole injection buffer layer between the metal electrodes and the polymer semiconductor film layer in OTFT devices. This buffer layer improved hole injection, while its use in the OTFT, improved the field-effect mobility significantly due to better matched energy levels between the electrodes and the polymer semiconductor.

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Electronic applications have expanded to encompass a variety of materials. In particular, allotropes of carbon interest researchers for their electronic applications. Knowledge of carbon allotropes and their applications has expanded significantly since the discovery of C60 Buckminsterfullerene in 1985, the discovery of multi- and single-walled carbon nanotubes in the early 1990s, and the isolation of graphene in 2004. Single-walled carbon nanotubes (SWNTs) have the potential to bring next-generation electronic devices to fruition. Such devices could be flexible, conformable, and inexpensive. SWNT-based electronics are promising for chemical and biological sensing applications, for example, where high carrier mobilities are unnecessary, and material conformity and inexpensive processing are significant advantages. Considerable progress has been made in separating semiconducting SWNTs from metallic SWNTs, enabling SWNT incorporation into semiconducting electronic technologies. Selective sorting of semiconducting SWNTs using π-conjugated polymers is an effective and efficient technique to enrich large quantities of ultra-pure semiconducting SWNTs. Following semiconducting enrichment, SWNTs can be incorporated into electronic devices. This thesis focuses on the enrichment of semiconducting SWNTs via conjugated polymer extraction and incorporating the resulting polymer-SWNT dispersions into thin-film transistors (TFTs). Novel copolymers were investigated for their capacity to selectively sort and disperse large-diameter sc-SWNTs synthesized using the plasma torch technique. Absorption and Raman spectroscopy were employed to monitor the efficacy of the conjugated polymer extraction procedure. Following enrichment, the polymer-SWNT dispersions were incorporated into TFTs. The interaction between the conjugated polymer and the SWNT and the conjugated polymer and dielectric was an essential component of TFT optimization. Furthermore, the procedure of sorting and dispersing sc-SWNTs is investigated for its effect on TFT performance and was another component of TFT optimization. TFTs were electrically characterized in terms of carrier mobility, threshold voltage, hysteresis, and current on/off ratio. The film morphology of the SWNT TFTs was also investigated. Atomic force microscopy and Raman mapping were used to provide insight into the nanometre and micrometre scale film morphology, respectively.

There has been a remarkable progress in the development of organic electronic materials since the discovery of conducting polymers more than three decades ago. Many of these materials can be processed from solution, in the form as inks. This allows for using traditional high-volume printing techniques for manufacturing of organic electronic devices on various flexible surfaces at low cost. Many of the envisioned applications will use printed batteries, organic solar cells or electromagnetic coupling for powering. This requires that the included devices are power efficient and can operate at low voltages. This thesis is focused on organic thin-film transistors that employ electrolytes as gate insulators. The high capacitance of the electrolyte layers allows the transistors to operate at very low voltages, at only 1 V. Polyanion-gated p-channel transistors and polycation-gated n-channel transistors are demonstrated. The mobile ions in the respective polyelectrolyte are attracted towards the gate electrode during transistor operation, while the polymer ions create a stable interface with the charged semiconductor channel. This suppresses electrochemical doping of the semiconductor bulk, which enables the transistors to fully operate in the field-effect mode. As a result, the transistors display relatively fast switching (≤ 100 µs). Interestingly, the switching speed of the transistors saturates as the channel length is reduced. This deviation from the downscaling rule is explained by that the ionic relaxation in the electrolyte limits the channel formation rather than the electronic transport in the semiconductor. Moreover, both unipolar and complementary integrated circuits based on polyelectrolyte-gated transistors are demonstrated. The complementary circuits operate at supply voltages down to 0.2 V, have a static power consumption of less than 2.5 nW per gate and display signal propagation delays down to 0.26 ms per stage. Hence, polyelectrolyte-gated circuits hold great promise for printed electronics applications driven by low-voltage and low-capacity power sources.

Graduation date: 2006 / A discrete trap model is developed and employed for elucidation of thin-film transistor (TFT) device physics trends. An attractive feature of this model is that only two model parameters are required, the trap energy depth, E[subscript T], and the trap density, N[subscript T]. The most relevant trends occur when E[subscript T] is above the Fermi level. For this case drain current – drain voltage simulations indicate that the drain current decreases with an increase in N[subscript T] and E[subscript T]. The threshold voltage, V[subscript T], extracted from drain current – gate voltage (I[subscript D] – V[[subscript GS]) simulations, is found to be composed of two parts, V[subscript TRAP], the voltage required to fill all the traps and V[subscript ELECTRON], the voltage associated with electrons populating the conduction band. V[subscript T] moves toward a more positive voltage as N[subscript T] and E[subscript T] increase. The inverse subthreshold voltage swing, S, extracted from a log(I[subscript D]) – V[subscript GS] curve, increases as N[subscript T] and E[subscript T] increase. Finally, incremental mobility and average mobility versus gate voltage simulations indicate that the channel mobility decreases with increasing N[subscript T] and E[subscript T].

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). <br /><br /> A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 &mu;m, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. <br /><br /> An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion.

Proteins are commonly found molecules in biological systems: our fingernails, hair, skin, blood, muscle, and eyes are all made of protein. Many diseases simply arise because a protein is not folded properly. Therefore, knowledge of protein structure is considered a prerequisite to understanding protein function and, by extension, a cornerstone for drug design and for the development of therapeutic agents. Protein crystallography is a tool that allows structural biologists to discern protein structures to the highest degree of detail possible in three dimensions. The recording of x-ray diffraction data from the protein crystal is a central part of protein crystallography. As such, an important challenge in protein crystallography research is to design x-ray detectors to accurately determine the structures of proteins. This research presents the design and evaluation of a solid-state large area at panel detector for protein crystallography based on an amorphous selenium (a-Se) x-ray sensitive photoconductor operating in avalanche mode integrated with an amorphous silicon (a-Si:H) charge storage and readout pixel. The advantages of the proposed detector over the existing imaging plate (IP) and charge coupled device (CCD) detectors are large area, high dynamic range coupled to single x-ray detection capability, fast readout, high spatial resolution, and inexpensive manufacturing process. The requirement of high dynamic range is crucial for protein crystallography since both weak and strong diffraction spots need to be imaged. The main disadvantage of a-Si:H thin film transistor (TFT) array is its high electronic noise which prohibits quantum noise limited operation for the weak diffraction spots. To overcome the problem, the x-ray to charge conversion gain of a-Se is increased by using its internal avalanche multiplication gain. Since the detector can be made approximately the same size as the diffraction pattern, it eliminates the need for image demagnification. The readout time of the detector is usually within the ms range, so it is appropriate for crystallographic application. The optimal detector parameters (such as, detector size, pixel size, thickness of a-Se layer), and operating parameters (such as, electric field across the a-Se layer) are determined based on the requirements for protein crystallography. A complete model of detective quantum efficiency (DQE) of the detector is developed to predict and optimize the performance of the detector. The performance of the detector is evaluated in terms of readout time (< 1 s), dynamic range (~10^5), and sensitivity (~ 1 x-ray photon), thus validating the detector's efficacy for protein crystallography. The design of an in-house a-Si:H TFT pixel array for integration with an avalanche a-Se layer is detailed. Results obtained using single pixel are promising and highlight the feasibility of a-Si:H pixels coupled with avalanche a-Se layer for protein crystallography application.

This report discuss the developement of a MATLAB-based tool for the analysis ofsurface area coverage of carbon nanotube networks from atomic force microscopyimages. The tool was compared with a manual method and the conclusion was that ithas, at least, the same accuracy as the manual mehtod, and it needs much less time forthe analysis. The tool couldn’t analyze images of carbon nanotube networks if theimages were to noisy or the networks to dense. The tool can help in the research ofthin-film transistors with carbon nanotube networks as the semiconducting channelmaterial.

The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). <br /><br /> A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 &mu;m, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. <br /><br /> An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion.