The target of this thesis is to fabricate through Silicon via (TSV) structures based on Si-bench technology for high-speed transmission interface. In this process, Si via with a depth of 250 £gm were formed by dry etching on a 500 £gm thick <111> Si wafer. The TSV were then obtained by removing the bottom of the silicon wafer using grinding technique. To reduce microwave loss of high frequency signal transmission, we oxidized the TSV by oxygen wet oxidation at a temperature of 1000 oC. Finally, conductive paths through the TSV were formed by filling silver epoxy into the via and dry at a temperature of 200 oC for 1 hour. The s parameters of the high speed TSV structure was characterized by a Vector Network Analyzer. Si-bench technology can effectively improve system integration and performance while reducing cost and size of the module package. . Key words: Through silicon via, microwave loss, s parameters

Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an improvement in power and performance, interconnect scaling results in a degradation in performance and electromigration reliability. Although graphene potentially has superior transport properties compared to copper, it is shown that several technology improvements like smooth edges, edge doping, good contacts, and good substrates are essential for graphene to outperform copper in high performance on-chip interconnect applications. However, for low power applications, the low capacitance of graphene results in 31\% energy savings compared to copper interconnects, for a fixed performance. Further, for characterization of the circuit parameters of multi-layer graphene, multi-conductor transmission line models that account for an alignment margin and finite width of the contact are developed. Although it is essential to push for an improvement in chip performance by improving on-chip interconnects, devices, and architectures, the system level performance can get severely limited by the bandwidth of off-chip interconnects. As a result, three dimensional integration and airgap interconnects are studied as potential replacements for conventional off-chip interconnects. The key parameters that limit the performance of a 3D IC are identified as the Through Silicon Via (TSV) capacitance, driver resistance, and on-chip wire resistance on the driver side. Further, the impact of on-chip wires on the performance of 3D ICs is shown to be more pronounced at advanced technology nodes and when the TSV diameter is scaled down. Airgap interconnects are shown to improve aggregate bandwidth by 3x to 5x for backplane and Printed Circuit Board (PCB) links, and by 2x for silicon interposer links, at comparable energy consumption.

With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area respectively. These concerns have led to an effort to find a solution that would reduce interconnect delay and leakage, while also reducing the area they occupy in a chip, so that either the chip area could be reduced, or more functionality could be incorporated within a certain area. 3D integration, i.e., stacking of various sub-systems of a chip on top of each other, enables chip-makers to achieve higher packaging efficiencies, thereby reducing system cost, while also reducing delay (and thus increasing the available bandwidth). Through Silicon Vias (TSVs) have emerged as the key interconnect technology for 3D ICs, as they enable significant reduction in delay and leakage compared to wire-bonded dies, while also occupying less area in a package. They also enable stacking of sub-systems which differ in functionality, and stacking of multiple dies. Also, unlike wire-bond, dies need not be bandwidth limited by the number of wire bonds that can be made between two levels in a stack. While TSVs offer many advantages, one of the concerns when implementing a 3D system using TSVs is the mechanisms of interaction between a TSV and a device in its vicinity. Another concern is with regards to the interaction between the TSV and its surrounding material. The purpose of this thesis is to develop a TCAD framework for process and device co-simulation of a TSV transistor system to study the various mechanisms of interaction between them, as well as between the TSV and substrate. The utility of this tool has been demonstrated by studying two mechanisms of interaction, the effect of TSV-induced stress, and the effect of TSV-device electrical coupling, on the electrical performance of bulk NMOS and PMOS transistors. The results from 3D TCAD simulations suggest that designers can scale the keep out zone (KOZ) around TSVs more aggressively, allowing for more efficient utilization of silicon area, without a drastic performance penalty.

Depuis plusieurs années, la complexité des circuits intégrés ne cesse d'augmenter : du SOC (System On Chip) vers le SIP (System In Package), et plus récemment les circuits empilés en 3D : les 3D SIC (Stacked Integrated Circuits) à base de TSVs (Through Silicon Vias) interconnectant verticalement les tiers, ou puces, du système. Les 3D SIC présentent de nombreux avantages en termes de facteur de forme, de performance et de consommation mais demandent aussi de relever de nombreux défis en ce qui concerne leur test, étape nécessaire avant la mise en service de ces systèmes complexes. Dans cette thèse, nous nous attachons à définir les infrastructures de test qui permettront de détecter les éventuels défauts apparaissant lors de la fabrication des TSVs ou des différentes puces du système. Nous proposons une solution de BIST (Built In Self Test) pour le test avant empilement des TSVs. Cette solution est basée sur l'utilisation d'oscillateurs en anneaux dont la fréquence d'oscillation dépend des caractéristiques électriques des TSVs. La solution de test proposée permet non seulement la détection de TSVs fautifs mais aussi de renseigner sur le nombre d'éléments défectueux et leur identification. D'autre part, nous proposons une architecture de test 3D basée sur la nouvelle proposition de norme IEEE P1687. Cette infrastructure permet de donner accès aux composants du système 3D avant et après empilement. Elle permet d'autre part de profiter du recyclage des données de test développées et appliquées avant empilement pour chacun des tiers puis ré-appliqués durant ou après l'empilement. Ces travaux aboutissent finalement à l'ouverture d'une nouvelle problématique liée à l'ordonnancement des tests sous contraintes (puissance consommée, température).Mots-clés : test, circuits 3D, TSV, BIST, oscillateur en anneau, architecture de test 3D, IEEE P1687, test avant empilement, test après empilement. / For several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test.

In this paper, processing effects of electroplating and post- plating annealing on via extrusion are investigated. The study is based on two TSV structures with identical geometry but different processing conditions. Via extrusion, stress and material behaviors of the TSV structures were first compared. Electron backscatter diffraction (EBSD) and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) were used to characterize the microstructure of TSVs and the additives incorporated during electroplating. Based on the results, processing effects on via extrusion and its mechanism are discussed, including grain growth, local plasticity, and diffusional creep.

abstract: To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed with superior electrical properties to traditional CMOS, such as strain technology and feedback field-effect transistor (FB-FET). To continue the design success and make an impact on leading products, advanced circuit design exploration must begin concurrently with early silicon development. Therefore, an accurate and scalable model is desired to correctly capture those effects and flexible to extend to alternative process choices. For example, strain technology has been successfully integrated into CMOS fabrication to improve transistor performance but the stress is non-uniformly distributed in the channel, leading to systematic performance variations. In this dissertation, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. On the other hand, semiconductor devices with self-feedback mechanisms are emerging as promising alternatives to CMOS. Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstances, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. A new threshold voltage model for Fe-FET is developed, and is further revealed that the impact of random dopant fluctuation (RDF) can be suppressed. Furthermore, through silicon via (TSV), a key technology that enables the 3D integration of chips, is studied. TSV structure is usually a cylindrical metal-oxide-semiconductors (MOS) capacitor. A piecewise capacitance model is proposed for 3D interconnect simulation. Due to the mismatch in coefficients of thermal expansion (CTE) among materials, thermal stress is observed in TSV process and impacts neighboring devices. The stress impact is investigated to support the interaction between silicon process and IC design at the early stage. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

京都大学 / 0048 / 新制・課程博士 / 博士(エネルギー科学) / 甲第22673号 / エネ博第405号 / 新制||エネ||77(附属図書館) / 京都大学大学院エネルギー科学研究科エネルギー応用科学専攻 / (主査)教授 平藤 哲司, 教授 馬渕 守, 教授 土井 俊哉 / 学位規則第4条第1項該当 / Doctor of Energy Science / Kyoto University / DFAM

Memory wall is becoming a more and more serious bottleneck of the processing speed of microprocessors. The mismatch between CPUs and memories has been increasing since three decades ago. SRAM was introduced as the bridge between the main memory and the CPU. SRAM is designed to be on the same die with CPU and stores temporary data and instructions that are to be processed by the CPU. Thus, the performance of SRAMs has a direct impact on the performance of CPUs. With the application of mass amount data to be processed nowadays, there is a great need for high-performance CPUs. Three dimensional CPUs and CPUs that are specifically designed for machine learning are gaining popularity. The objective of this work is to design high-performance SRAM for these two emerging applications. Firstly, a novel delay cell based on dummy TSV is proposed to replace traditional delay cells for better timing control. Secondly, a unique SRAM with novel architecture is custom designed for a high-performance machine learning processor. Post-layout simulation shows that the SRAM works well with the processing core and its design is optimized to work well with machine learning processors based on convolutional neural networks. A prototype of the SRAM is also tapped out to further verify our design.

Les FPGAs (Field Programmable Gate Arrays) sont aujourd'hui des acteurs fondamen-taux dans le domaine des calculateurs qui etait auparavant domin par les microprocesseurs et les ASICs. Le principal enjeu de la conception de FPGA est de trouver le bon compromis entre les performances et la exibilite. Les caractristiques d'un FPGA dependent de trois facteurs : la qualite de l'architecture, la qualite des outils permettant d'implantes l'application sur le FPGA et la technologie utilisee. Le but de cette thse est de proposer une methodologie de conception pour la realisation physique de FPGA en technologie 3 dimensions (3D) ainsi que les outils d'exploration architecturale pour l'empilement en 3D du FPGA arborescent an d'ameliorer lses performances en terme de surface, densite, consommation et vitesse.La premiere partie du manuscrit etudie les dierentes variantes des architectures 2D du FPGA arborescent et l'impact de la migration vers la technologie 3D sur leur topologie. Nous presentons de nombreuses etudes montrant les caracteristiques des reseaux d'interconnexion arborescents, comment ils se comportent en terme de surface et per- formances et comment ils tiennent compte des particularites de l'applicationablee. Mal- heureusement, nous n'avons jamais vu d'avancees en ce qui concerne l'optimisation de telles topologies an d'exploiter leur avantage en terme de surface et consommation, ou encore de resoudre le probleme de longueur des ls qui entrave leurs performances. Tout au long de ce travail, nous avons compris qu'il ne serait pas possible d'optimiser la vitesse sans s'attaquer a la structure m^eme du reseau d'interconnexion arborescent pour l'exploiter a nouveau gr^ace a la technologie 3D. Ce type de technologie peut reduire les problemes de delai du reseau d'interconnexion en orant davantage de exibilite a la conception, au placement et au routage. Un ensemble d'outil d'exploration d'architectures 3D de FPGA a ete developpe pour valider les avancees en terme de performances et surface.La seconde contribution de cette these est le developpement d'une methodologie de conception de circuits FPGA 3D ainsi que l'utilisation des outils de conception classiques (en 2D) pour la realisation physique d'un FPGA arborescent 3D. Tout au long du processus de conception, nous avons ete confrontes aux nombreux problemes que rencontrent les concepteurs 3D en utilisant des outils qui ne sont pas connus pour leurs besoins. De plus, l'utilisation de la technologie 3D risque d'aggraver les performances thermiques. Nous examinons alors precisement l'evolution du comportement thermique lie a l'integration 3D et nous avons montrons comment le contrler en utilisant des techniques de conception tenant compte de la temprature. / Today, FPGAs (Field Programmable Gate Arrays) has become important actors in the computational devices domain that was originally dominated by microprocessors and ASICs. FPGA design big challenge is to nd a good trade-o between exibility and performances. Three factors combine to determine the characteristics of an FPGA: quality of its architecture, quality of the CAD tools used to map circuits into the FPGA, and its electrical technology design. This dissertation aims at exploring a development of Three- dimensional (3D) physical design methodology and exploration tools for 3D Tree-based stacked FPGA architecture to improve area, density, power and performances. The first part of the dissertation is to study the existing variants of 2D Tree-based FPGA architecture and the impact of 3D migration on its topology. We have seen numerous studies showing the characteristics of Tree-based interconnect networks, how they scale in terms of area and performance, and empirically how they relate to particular designs. Nevertheless we never had any breakthrough in optimizing these network topologies to exploit the advantages in area and power consumption and how to deal with the larger wire-length issues that impede performance of Tree-based FPGA architecture. Through the course of the work, we understand that, we would not be able to optimize the speed, unless we break the very backbone of the Tree-based interconnect network and resurrect again by using 3D technology. The 3D-ICs can alleviate interconnect delay issues by ofering exibility in system design, placement and routing. A new set of 3D FPGA architecture exploration tools and technologies developed to validate the advance in performance and area.The second contribution of this thesis is the development 3D physical design methodology and tools using existing 2D CAD tools for the implementation of 3D Tree-based FPGA demonstrator. During the course of design process, we addressed many specic issues that 3D designers will encounter dealing with tools that are not specically designed to meet their needs. In contrast, the thermal performance is expected to worsen with the use of 3D integration. We examined precisely how thermal behavior scales in 3D integration and determine how the temperature can be controlled using thermal design techniques.

3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore’s law trajectory. 3D Integrated Circuits (ICs) can be realized using the Through Silicon Via (TSV) approach. In order to extract the full benefits of 3D and for better yield, it has been suggested that the TSVs should be arranged as bundles rather than parallel TSVs. TSVs are required to route the signals through different dies in a multi-tier 3D IC. TSVs are excellent but scarce electrical conductors. Hence, it is important to utilize these resources very efficiently. In high performance 3D ICs, signaling techniques play a crucial role in determining the overall performance of the system. In this work, 3x3 and 4x4 TSV bundles are considered. Electrical parasitics of TSV bundles are extracted using Ansoft Q3D Extractor. Various techniques for signaling over TSV bundles are analyzed in this work. Performance, energy and robustness are the crucial aspects to be considered for analyzing a signaling technique. For performance analysis, maximum data rate for each of the signaling techniques is obtained and the dominant factors that determine these values are identified. 3D integration is fairly a new field and does not have common standards. Different research groups (both academic and industry) across the globe have different manufacturing technologies to suit their needs. In this work, we obtain the electrical parasitics of TSV bundles for different TSV radii ranging from 1mm to 15mm. The TSV radius for most of the 3D integration technologies falls within this range. Maximum data rates are determined for different TSV radii ranging from 1mm to 15mm. This study across different TSV radii helps in choosing a better signaling technique for a particular TSV radius depending on the design goals. Energy/bit for each of the signaling techniques is obtained for a common data rate of 10Gbps Pseudo Random Bit Sequence (PRBS) input. For robustness analysis, the impact of process, voltage and temperature variations between driver and receiver circuits is analyzed. Ansoft Q3D extractor, NCSU 45nm PDK and HSPICE simulation tool are used. From the simulation results, it is observed that a differential technique is beneficial for smaller radii in terms of maximum data rate that can be obtained. For a radius above 7mm, single ended current mode signaling gives a better data rate. Low swing single ended signaling techniques consume less energy but suffer slightly more due to process variations compared to full swing voltage mode signaling. In terms of robustness to supply noise, differential signaling is more robust compared to single ended techniques. An increase in the temperature reduces the data rates of both single ended and differential signaling techniques. Hence, depending on the TSV radius of target technology and process and environment variations, an optimum signaling technique can be chosen.