This thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is also presented. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. A discussion of the different methods of bandwidth extension using inductive peaking is included, and the optimal configurations for maximally flat responses are shown for shunt inductive peaking,series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology is optimized using a novel noise analysis that uses a high frequency noise model for the transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-07-16 13:34:41.46

The combination of silicon photonics and advanced heterogeneous integration is promising for next-generation disaggregated data centers that demand large scale, high throughput, and low power. In this dissertation, we discuss the design and theory of power-efficient optical transceivers with System-in-Package (SiP) 2.5D integration. Combining prior arts and proposed circuit techniques, a receiver chip and a transmitter chip including two 10 Gb/s data channels and one 2.5 GHz clocking channel are designed and implemented in 28 nm CMOS technology. An innovative transimpedance amplifier (TIA) and a single-ended to differential (S2D) converter are proposed and analyzed for a low-voltage high-sensitivity receiver; a four-to-one serializer, programmable output drivers, AC coupling units, and custom pads are implemented in a low-power transmitter; an improved quadrature locked loop (QLL) is employed to generate accurate quadrature clocks. In addition, we present an analysis for inverter-based shunt-feedback TIA to explicitly depict the trade-off among sensitivity, data rate, and power consumption. At last, the research on CDR-based​ clocking schemes for optical links is also discussed. We introduce prior arts and propose a power-efficient clocking scheme based on an injection-locked phase rotator. Next, we analyze injection-locked ring oscillators (ILROs) that have been widely used for quadrature clock generators (QCGs) in multi-lane optical or wireline transceivers due to their low power, low area, and technology scalability. The asymmetrical or partial injection locking from 2 phases to 4 phases results in imbalances in amplitude and phase. We propose a modified frequency-domain analysis to provide intuitive insight into the performance design trade-offs. The analysis is validated by comparing analytical predictions with simulations for an ILRO-based QCG in 28 nm CMOS technology. This dissertation also discusses the design of high-linearity wireless wideband receivers. An out-of-band (OB) IM3 cancellation technique is proposed and analyzed. By exploiting a baseband auxiliary path (AP) with a high-pass feature, the in-band (IB) desired signal and out-of-band interferers are split. OB third-order intermodulation products (IM3) are reconstructed in the AP and cancelled in the baseband (BB). A 0.5-2.5 GHz frequency-translational noise-cancelling (FTNC) receiver is implemented in 65nm CMOS to demonstrate the proposed approach. It consumes 36 mW without cancellation at 1 GHz LO frequency and 1.2 V supply, and it achieves 8.8 MHz baseband bandwidth, 40dB gain, 3.3dB NF, 5dBm OB IIP3, and −6.5dBm OB B1dB. After IM3 cancellation, the effective OB-IIP3 increases to 32.5 dBm with an extra 34 mW for narrow-band interferers (two tones). For wideband interferers, 18.8 dB cancellation is demonstrated over 10 MHz with two −15 dBm modulated interferers. The local oscillator (LO) leakage is −92 dBm and −88 dB at 1 GHz and 2 GHz LO respectively. In summary, this technique achieves both high OB linearity and good LO isolation.

No description available.

Circuits to extend operation data-rate of a optical receiver is investigated in the dissertation. A new input-stage topology for a transimpedance amplifier (TIA) is designed to achieve 50% higher data-rate is presented, and a new architecture for clock recovery is proposed for 50% higher clock rate. The TIA is based on a gm-boosted common-gate amplifier. The input-resistance is reduced by modifying a transistor at input stage to be diode-connected, and therefore lowers R-C time constant at the input and yielding higher input pole frequency. It also allows removal of input inductor, which reduces design complexity. The proposed circuit was designed and fabricated in 32 nm CMOS SOI technology. Compared to TIAs which mostly operates at 50 GHz bandwidth or lower, the presented TIA stage achieves bandwidth of 74 GHz and gain of 37 dBohms while dissipating 16.5 mW under 1.5V supply voltage. For the clock recovery circuit, a phase-locked loop is designed consisting of a frequency doubling mechanism, a mixer-based phase detector and a 40 GHz voltage-controlled oscillator. The proposed frequency doubling mechanism is an all-analog architecture instead of the conventional digital XOR gate approach. This approach realizes clock-rate of 40 GHz, which is at least 50% higher than other circuits with mixer-based phase detector. Implemented with 0.13-μm CMOS technology, the clock recovery circuit presents peak-to-peak clock jitter of 2.38 ps while consuming 112 mW from a 1.8 V supply. / Ph. D. / This dissertation presents two electronic circuits for future high-speed fiber optics applications. A receiver in a optical communication systems includes several circuit blocks serving various functions: (1) a photodiode for detecting the input signal; (2) a transimpedance amplifier (TIA) to amplify the input signal; (3) a clock and data recovery block to re-condition the input signal; and (4) digital signal processing. High speed integrated circuits are commonly fabricated in SiGe or other high electron mobility semiconductor technologies, but receiver circuits based on Silicon using complementary metal oxide semiconductor (CMOS) technology has gained attention in open literatures due to its advantage of integrating signal processing . This dissertation shows a TIA circuit and a clock recovery circuit designed and implemented in CMOS technology. The TIA circuit is based on a ”g_m-boosted common-gate amplifier” topology, and a slight modification at the input of the topology is proposed. Implemented in 32nm SOI CMOS technology, the TIA measures bandwidth that achieved 100 Gb/s bandwidth. The bandwidth is increased by at least 48% when compared with state-of-the-art CMOS TIA’s. The clock recovery circuit is a phase-locked loop with a mixer as the phase detector. An architectural change of replacing the conventional frequency doubling mechanism is proposed. The circuit is implemented in 0.13 µm CMOS technology, and it achieved 40 GHz clock rate with 40 Gb/s data input, which is about 40% increase of clock rate compared to state-of-the-art clock recovery circuits of similar architecture.

The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors. The MEMS sensor used in this work is an in-plane bulk-micromachined mode-matched tuning fork gyroscope (M² – TFG ), fabricated on silicon-on-insulator substrate. The use of CMOS transimpedance amplifiers (TIA) as front-ends in high-Q MEMS resonant sensors is explored. A T-network TIA is proposed as the front-end for resonant capacitive detection. The T-TIA provides on-chip transimpedance gains of 25MΩ, has a measured capacitive resolution of 0.02aF /√Hz at 15kHz, a dynamic range of 104dB in a bandwidth of 10Hz and consumes 400μW of power. A second contribution is the development of an automated scheme to adaptively bias the mechanical structure, such that the sensor is operated in the mode-matched condition. Mode-matching leverages the inherently high quality factors of the microgyroscope, resulting in significant improvement in the Brownian noise floor, electronic noise, sensitivity and bias drift of the microsensor. We developed a novel architecture that utilizes the often ignored residual quadrature error in a gyroscope to achieve and maintain perfect mode-matching (i.e.0Hz split between the drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS implementation is developed that allows mode-matching of the drive and sense frequencies of a gyroscope at a fraction of the time taken by current state of-the-art techniques. Further, this mode-matching technique allows for maintaining a controlled separation between the drive and sense resonant frequencies, providing a means of increasing sensor bandwidth and dynamic range. The mode-matching CMOS IC, implemented in a 0.5μm 2P3M process, and control algorithm have been interfaced with a 60μm thick M2−TFG to implement an angular rate sensor with bias drift as low as 0.1°/hr ℃ the lowest recorded to date for a silicon MEMS gyro.

This work is focused on free space optical communication in visible electromagnetic spectrum known as visible light communication (VLC). Basic parameters of standard IEEE 802.15.7, advantages and disadvantages are discussed in the theoretical part of this work. Furthermore, optical link and it´s parts are described. The largest part of the work is focused on design and simulation of optical receiver for visible spectrum. Selection of component, noise and SNR calculation is discussed as well. This work also includes calculation of power energy in different parts of optical connection, PCB design of optical receiver, transmitters and power supply and output board. Behavior and parameters of electronic circuits, components and optical connection are explored, measured and compared with theoretical values.

Measuring low electrical currents with high precision is critical across various fields, particularly in applications like microfluidic biosensing. Traditional digital multimeters (DMMs) are inadequate for low current measurements due to their high input burden and limited resolution. Therefore, more sensitive instruments like electrometers and picoammeters are often required but are typically expensive. This thesis explores the design and construction of a cost-effective, portable, and user-friendly picoammeter based on a transimpedance amplifier (TIA), capable of measuring currents in the picoampere (pA) range with a resolution of 1-5 pA and minimal noise. The constructed picoammeter has a maximum input current range of ±1.5 nA.  A prototype was built on a soldering board to validate the design, which was then translated into a practical printed circuit board (PCB) layout. The device is powered by batteries to ensure low noise levels and enable isolated operation. An Arduino microcontroller was used to interface with the circuit, manage data acquisition, and enable real-time visualisation of the measured current data on a computer.  Simulation results confirmed the theoretical performance of the circuit, and experimental validation showed RMS noise levels of less than 0.3 pA under controlled conditions and up to 3 pA when measuring streaming currents from a microchip. Despite a slight underestimation of input currents due to resistor tolerances, calibration adjustments successfully corrected these discrepancies.  The total cost of the materials used in constructing the picoammeter was significantly less than the cost of commercially available devices. While commercial devices offer higher precision and additional functionalities, the developed picoammeter demonstrates how application-focused solutions can provide comparable accuracy and noise characteristics to commercial devices for a fraction of the price.

This master's thesis deals with the design of a differential high-gain transimpedance amplifier in TSMC's 0.18 um mixed signal process that utilizes a DC photodiode current cancellation loop and a switching automatic gain control (AGC) with a bilinear gain curve. The amplifier is designed to satisfy the demands of Optical Coherence Tomography applications where the receiver is expected to measure the envelope power of an amplitude modulated sinusoidal optical signal that incorporates a large DC component. Methods of increasing dynamic range and gain linearity through the use of DC photodiode current cancellation and bilinear gain are explored. Effects of changing DC photodiode current on the overall system response is also demonstrated.

Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies. The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER. Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications.

La thèse porte sur les mesures de courants transitoires limités par la charge d'espace dans des films minces organiques (épaisseur < 500 nm). Ce type de films est souvent utilisé dans des applications dans le domaine de l'électronique organique comme couches actives semi-conductrices. Le transport électrique dans ces films dépend en premier lieu du transport des porteurs de charge dans le milieu massif et de leur piégeage, mais aussi de l'efficacité de l'injection des porteurs de charges à partir des électrodes métalliques. L'ensemble est de plus conditionné par le taux de désordre inhérent aux matériaux organiques. L'approche qui consiste à utiliser la mesure de courants transitoires est extrêmement attractive car elle permet en principe de fournir une information sur tous ces aspects à l'issue d'un seul type de mesure. Dans ce cadre, trois contributions principales peuvent être dégagées de la thèse. 1) Tout d'abord, nous avons validé un montage expérimental qui utilise un amplificateur à transfert d'impédance pour la mesure des courants transitoires limités par la charge d'espace. Ce type de montage s'avère supérieur au circuit de pont électrique le plus largement utilisé jusqu'à maintenant car il présente une meilleure sensibilité en courant, une meilleure bande passante, et ne nécessite aucun réglage ni de la symétrie du pont ni de l'ajustement de la taille de l'échantillon. On a pu démontrer que le pic de courant de déplacement initial, qui sature l'amplificateur au tout début de la mesure n'introduit pas d'erreur dans la mesure de la mobilité. 2) Ensuite concernant l'étude plus spécifique du transport dans un dendrimère à base de tri-arylamine, les réponse en courant obtenues expérimentalement se sont avérées en bon accord avec le modèle de déplacement-diffusion. Cependant, la troisième leçon que nous avons apprise est que l'obtention d'un tel accord a nécessité que soient très bien définies les conditions initiales tant de l'expérience que de la simulation et qu'un modèle théorique le plus complet possible de l'échantillon soit considéré. Pour le dendrimère ce modèle a dû prendre en compte l'effet de la barrière au contact et les effets de piégeage. Un accord encore meilleur a été obtenu en intégrant de surcroit les effets de désordre. 3) La complète impossibilité d'obtenir un bon accord sans un modèle physique complet de l'échantillon indique que les paramètres liés au piégeage, à la barrière au contact et à la mobilité peuvent véritablement être ajustés sans aucune ambigüité. Ainsi, une caractérisation électrique complète en cohérence avec la simulation a pu être obtenue à l'issue d'un seul type de mesures. Les résultats obtenus, alliant à la fois amélioration technique et support numérique, témoignent de la grande utilité de cette technique de mesure de courant transitoire limité par la charge d'espace pour caractériser en détails le transport dans les films minces organiques. / The thesis concerns space-charge-limited transient current measurements in thin (le500 nm) organic films. Such films find important applications in organic electronics, where they are referred to as organic semiconductor layers. Electrical transport in such films depends on bulk charge carrier transport and trapping, as well efficiency of charge carrier injection from electrodes. These, are all in turn depend on disorder inherent to organic materials. The transient measurement approach is very attractive, as it can, in principle, deliver information on all these aspects in one single measurement. In the thesis, three main contributions are presented. 1) A transimpedance amplifier based setup for space-charge-limited current transient measurement is validated. This type of setup is superior to the widely used bridge circuit, notably because of better current sensitivity, bandwidth, no need for bridge symmetry and no need for per sample adjustment. It is demonstrated that initial displacement current spike, which saturates the amplifier at the beginning of measurement, does not introduce error in the measurement of mobility. 2) A dendrimer molecule has been investigated. Experimental current responses are shown to be in agreement with the drift-diffusion model. However, obtaining agreement requires well defined initial conditions in experiment as well as in simulation, and also complete theoretical model of the sample. In the case of dendrimer, this model had to take into account both contact barrier and trapping effects. Furthermore, better agreement was obtained when taking disorder effects into account. 3) The impossibility of obtaining any agreement without complete physical model of the sample indicates that trapping, contact barrier and mobility parameters could be fitted without ambiguity. Therefore, complete electrical characterization consistent with simulation can be obtained using the transient technique. The results obtained further increase well known usefulness of transient space-charge-limited current characterization of thin organic films.