In der vorliegenden Arbeit wird die Steifigkeits- und Festigkeitsauslegung von mittels der Tailored Fiber Placement (TFP)-Technologie hergestellten Faser-Kunststoff-Verbunden (FKV) am Beispiel eines einteiligen Rotors aus kohlenstofffaserverstärktem Epoxidharz (CFK) für den Einsatz in Turbomolekularpumpen (TMP) vorgestellt. Im Vergleich zu anderen textilen Fertigungsverfahren können mit Hilfe der TFP-Technologie Verstärkungsfaserrovings in der Ebene variabelaxial, d. h. mit ortsunabhängiger, frei wählbarer Richtung, definiert abgelegt werden. Die sticktechnische Fixierung der Rovings mit Hilfe eines Nähfadens führt zu Welligkeiten und Materialinhomogenitäten in TFP-basierten Faser-Kunststoff-Verbunden (FKV). Dadurch werden die Materialeigenschaften beeinflusst. Mit Hilfe einer Prozessanalyse in Kombination mit morphologischen Untersuchungen werden in dieser Arbeit die welligkeitsinduzierenden Effekte in TFP-basierten FKV identifiziert und quantifiziert. Darauf aufbauend wird ein mesoskaliges Repräsentatives Volumenelement (RVE) einer TFP-Einheitszelle auf Basis von Finiten Elementen entwickelt. Mit Hilfe des RVE wird es erstmalig ermöglicht, die Dehnungs- und Spannungsverteilung sowie den lokalen Faservolumengehalt in TFP-basierten FKV zu berechnen und daraus wirklichkeitsnahe Materialkennwerte abzuleiten. Darüber hinaus wird anhand des RVE der Einfluss variierender TFP-Prozessparameter auf die resultierenden Steifigkeits- und Festigkeitseigenschaften analysiert. Weiterhin wird der Einfluss des unter Langzeitbelastung eintretenden Matrixkriechens auf die Materialeigenschaften von TFP-basierten FKV untersucht. Anhand der Entwicklungsschritte eines CFK-TMP-Rotordemonstrators werden die Besonderheiten beim Auslegungsprozess für Bauteile aus TFP-Strukturen verdeutlicht. Neben der Erläuterung der Lastfälle von TMP-Rotoren wird die Entwicklung eines lastfallangepassten Faserlayouts unter Berücksichtigung von geometrischen Restriktionen beschrieben. Im Rahmen der Spannungsanalyse auf Basis der Finite Elemente Methode (FEM) erfolgt die Integration der mittels des RVE bestimmten Materialdaten in das FE-Modell schichtweise, entsprechend der verwendeten TFP-Prozessparameter. Die mit dieser Vorgehensweise berechnete Versagensdrehzahl und die ermittelten Eigenfrequenzen konnten in experimentellen Untersuchungen erfolgreich validiert werden. Durch die Integration der ortsaufgelösten RVE-basierten Materialdaten wird erstmalig nicht nur die Struktursteifigkeit, sondern auch die Festigkeit ausgehend von einem variabelaxialen TFP-Ablagemuster in einem TFP-basierten Bauteil vorhergesagt. Mit dem entwickelten TMP-Rotordemonstrator kann die Versagensdrehzahl gegenüber dem Stand der Technik um 45 % gesteigert werden. In der Arbeit wird auch herausgestellt, welche Änderungen der Geometrie von TMP-Rotoren aus FKV nötig sind, um eine werkstoffgerechte, an die orthotropen Eigenschaften von FKV angepasste Gestaltung zu realisieren und damit die Nenndrehzahlen weiter steigern zu können. Diese Erkenntnisse dienen in verallgemeinerter Weise der werkstoffgerechten Auslegung und Fertigung von TFP-basierten FKV-Bauteilen. / The present work demonstrates the stiffness and strength design of fiber reinforced plastics (FRP) made by the Tailored Fiber Placement (TFP) technology using the example of a a turbo molecular pump (TMP) rotor made of carbon fiber reinforced epoxy resin (CFRP). In contrast to other textile preform manufacturing processes, the TFP technology enables the placement of reinforcement rovings in arbitrary direction according to an user defined design path. In this technology a double locked stitch in a zigzag stitch pattern is used to fixate the rovings. The fixation process leads to waviness and material inhomogeneities within the placed rovings resulting in reduced material properties in TFP-based fiber reinforced plastics. The wavinessinducing effects have been identified and quantified by detailed process analysis and morphological investigations. Subsequently, a meso-scaled representative volume element (RVE) of a TFP unit cell based on finite elements was developed. The RVE provides the opportunity to derive realistic material properties by calculating the stress and strain distribution as well as as the local fiber content in TFP-based FRP. In this work, the influence of different TFP process parameters on the resulting modulus and strength has been investigated using the RVE approach. Additionally, long term loading effects leading to a reduced matrix modulus were analyzed numerically with the RVE. Based on the development of the CFRP TMP rotor specific characteristics of the design process for components made of TFP are clarified. Besides the explanation of loading conditions of TMP rotors the progress of a load-adapted fiber layout considering geometrical restrictions is demonstrated. For the stress analysis based on the Finite Element Method (FEM) material data calculated with the RVE according to the applied TFP process parameters have been integrated into the FE model. The numerically determined failure speed and the calculated eigenfrequencies were successfully validated by experimental tests. By implementing TFP specific material data in the FE model, both, the strucural rigidity as well as the strength, were predicted for the first time in a TFP-based component. Compared to the state-of-the-art, the developed TMP rotor offers an increased failure speed by 45 %. Furthermore necessary geometric modifications for FRP based TMP rotors in order to achieve a material-specific design adapted to the orthotropic material properties and thus to further increase the nominal rotational speeds were shown. These findings provide in a generalized way for a material-specific design of TFP-based FRP components.

Les systèmes de téléphonie mobile de 4ème et 5ème générations ont adopté comme techniques de codage de canal les turbocodes, les codes LDPC et les codes polaires binaires. Cependant, ces codes ne permettent pas de répondre aux exigences, en termes d’efficacité spectrale et de fiabilité, pour les réseaux de communications futurs (2030 et au-delà), qui devront supporter de nouvelles applications telles que les communications holographiques, les véhicules autonomes, l’internet tactile … Un premier pas a été fait il y a quelques années vers la définition de codes correcteurs d’erreurs plus puissants avec l’étude de codes LDPC non binaires, qui ont montré une meilleure performance que leurs équivalents binaires pour de petites tailles de code et/ou lorsqu'ils sont utilisés sur des canaux non binaires. En contrepartie, les codes LDPC non binaires présentent une complexité de décodage plus importante que leur équivalent binaire. Des études similaires ont commencé à émerger du côté des turbocodes. Tout comme pour leurs homologues LDPC, les turbocodes non binaires présentent d’excellentes performances pour de petites tailles de blocs. Du point de vue du décodage, les turbocodes non binaires sont confrontés au même problème d’augmentation de la complexité de traitement que les codes LDPC non binaire. Dans cette thèse nous avons proposé une nouvelle structure de turbocodes non binaires en optimisant les différents blocs qui la constituent. Nous avons réduit la complexité de ces codes grâce à la définition d’un algorithme de décodage simplifié. Les codes obtenus ont montré des performances intéressantes en comparaison avec les codes correcteur d’erreur de la littérature. / Nowadays communication standards have adopted different binary forward error correction codes. Turbo codes were adopted for the long term evolution standard, while binary LDPC codes were standardized for the fifth generation of mobile communication (5G) along side with the polar codes. Meanwhile, the focus of the communication community is shifted towards the requirement of beyond 5G standards. Networks for the year 2030 and beyond are expected to support novel forward-looking scenarios, such as holographic communications, autonomous vehicles, massive machine-type communications, tactile Internet… To respond to the expected requirements of new communication systems, non-binary LDPC codes were defined, and they are shown to achieve better error correcting performance than the binary LDPC codes. This performance gain was followed by a high decoding complexity, depending on the field order.Similar studies emerged in the context of turbo codes, where the non-binary turbo codes were defined, and have shown promising error correcting performance, while imposing high complexity. The aim of this thesis is to propose a new low-complex structure of non-binary turbocodes. The constituent blocks of this structure were optimized in this work, and a new low complexity decoding algorithm was proposed targeting a future hardware implementation. The obtained results are promising, where the proposed codes are shown to outperform existing binary and non-binary codes from the literature.

Le codage de sources distribuées est une technique permettant de compresser plusieurs sources corrélées sans aucune coopération entre les encodeurs, et sans perte de débit si leur décodage s'effectue conjointement. Fort de ce principe, le codage de vidéo distribué exploite la corrélation entre les images successives d'une vidéo, en simplifiant au maximum l'encodeur et en laissant le décodeur exploiter la corrélation. Parmi les contributions de cette thèse, nous nous intéressons dans une première partie au codage asymétrique de sources binaires dont la distribution n'est pas uniforme, puis au codage des sources à états de Markov cachés. Nous montrons d'abord que, pour ces deux types de sources, exploiter la distribution au décodeur permet d'augmenter le taux de compression. En ce qui concerne le canal binaire symétrique modélisant la corrélation entre les sources, nous proposons un outil, basé sur l'algorithme EM, pour en estimer le paramètre. Nous montrons que cet outil permet d'obtenir une estimation rapide du paramètre, tout en assurant une précision proche de la borne de Cramer-Rao. Dans une deuxième partie, nous développons des outils permettant de décoder avec succès les sources précédemment étudiées. Pour cela, nous utilisons des codes Turbo et LDPC basés syndrome, ainsi que l'algorithme EM. Cette partie a été l'occasion de développer des nouveaux outils pour atteindre les bornes des codages asymétrique et non-asymétrique. Nous montrons aussi que, pour les sources non-uniformes, le rôle des sources corrélées n'est pas symétrique. Enfin, nous montrons que les modèles de sources proposés modélisent bien les distributions des plans de bits des vidéos; nous montrons des résultats prouvant l'efficacité des outils développés. Ces derniers permettent d'améliorer de façon notable la performance débit-distorsion d'un codeur vidéo distribué, mais sous certaines conditions d'additivité du canal de corrélation.

du fait de l'explosion actuelle des télécommunications, les opérateurs sont victimes d'une crise de croissance les obligeant à installer toujours plus de relais, à découper les cellules (zone de couverture d'un relais) en micro-cellules dans les grandes villes, afin de faire face à la demande toujours grandissante de communications. Les concepteurs des nouveaux réseaux de transmission sont donc constamment à la recherche d'une utilisation plus efficace des ressources disponibles

<p>This thesis consists of four papers and a summary. The common topic of the included papers are the pricing equations of path-dependent options. Various properties of barrier options and American options are studied, such as convexity of option prices, the size of the continuation region in American option pricing and pricing formulas for turbo warrants. In Paper I we study the effect of model misspecification on barrier option pricing. It turns out that, as in the case of ordinary European and American options, this is closely related to convexity properties of the option prices. We show that barrier option prices are convex under certain conditions on the contract function and on the relation between the risk-free rate of return and the dividend rate. In Paper II a new condition is given to ensure that the early exercise feature in American option pricing has a positive value. We give necessary and sufficient conditions for the American option price to coincide with the corresponding European option price in at least one diffusion model. In Paper III we study parabolic obstacle problems related to American option pricing and in particular the size of the non-coincidence set. The main result is that if the boundary of the set of points where the obstacle is a strict subsolution to the differential equation is C¹-Dini in space and Lipschitz in time, there is a positive distance, which is uniform in space, between the boundary of this set and the boundary of the non-coincidence set. In Paper IV we derive explicit pricing formulas for turbo warrants under the classical Black-Scholes assumptions.</p>

This thesis consists of four papers and a summary. The common topic of the included papers are the pricing equations of path-dependent options. Various properties of barrier options and American options are studied, such as convexity of option prices, the size of the continuation region in American option pricing and pricing formulas for turbo warrants. In Paper I we study the effect of model misspecification on barrier option pricing. It turns out that, as in the case of ordinary European and American options, this is closely related to convexity properties of the option prices. We show that barrier option prices are convex under certain conditions on the contract function and on the relation between the risk-free rate of return and the dividend rate. In Paper II a new condition is given to ensure that the early exercise feature in American option pricing has a positive value. We give necessary and sufficient conditions for the American option price to coincide with the corresponding European option price in at least one diffusion model. In Paper III we study parabolic obstacle problems related to American option pricing and in particular the size of the non-coincidence set. The main result is that if the boundary of the set of points where the obstacle is a strict subsolution to the differential equation is C1-Dini in space and Lipschitz in time, there is a positive distance, which is uniform in space, between the boundary of this set and the boundary of the non-coincidence set. In Paper IV we derive explicit pricing formulas for turbo warrants under the classical Black-Scholes assumptions.

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

In this thesis, we present low latency general concatenated code structures suitable for parallel processing. We propose parallel decodable serially concatenated codes (PDSCCs) which is a general structure to construct many variants of serially concatenated codes. Using this most general structure we derive parallel decodable serially concatenated convolutional codes (PDSCCCs). Convolutional product codes which are instances of PDSCCCs are studied in detail. PDSCCCs have much less decoding latency and show almost the same performance compared to classical serially concatenated convolutional codes. Using the same idea, we propose parallel decodable turbo codes (PDTCs) which represent a general structure to construct parallel concatenated codes. PDTCs have much less latency compared to classical turbo codes and they both achieve similar performance. We extend the approach proposed for the construction of parallel decodable concatenated codes to trellis coded modulation, turbo channel equalization, and space time trellis codes and show that low latency systems can be constructed using the same idea. Parallel decoding operation introduces new problems in implementation. One such problem is memory collision which occurs when multiple decoder units attempt accessing the same memory device. We propose novel interleaver structures which prevent the memory collision problem while achieving performance close to other interleavers.

A non-iterative receiver is proposed to achieve near capacity performance on intersymbol interference (ISI) channels. There are two main ingredients in the proposed design. i) The use of a novel BCJR-DFE equalizer which produces optimal soft estimates of the inputs to the ISI channel given all the observations from the channel and L past symbols exactly, where L is the memory of the ISI channel. ii) The use of an encoder structure that ensures that L past symbols can be used in the DFE in an error free manner through the use of a capacity achieving code for a memoryless channel. Computational complexity of the proposed receiver structure is less than that of one iteration of the turbo receiver. We also provide the proof showing that the proposed receiver achieves the i.i.d. capacity of any constrained input ISI channel. This DFE-based receiver has several advantages over an iterative (turbo) receiver, such as low complexity, the fact that codes that are optimized for memoryless channels can be used with channels with memory, and finally that the channel does not need to be known at the transmitter. The proposed coding scheme is universal in the sense that a single code of rate r; optimized for a memoryless channel, provides small error probability uniformly across all AWGN-ISI channels of i.i.d. capacity less than r: This general principle of a proposed non-iterative receiver also applies to other signal processing functions, such as timing recovery, pattern-dependent noise whiten ing, joint demodulation and decoding etc. This makes the proposed encoder and receiver structure a viable alternative to iterative signal processing. The results show significant complexity reduction and performance gain for the case of timing recovery and patter-dependent noise whitening for magnetic recording channels.

The main objective of this thesis is to propose new methods for designing high-performance embedded computer system architectures. To achieve the goal, three major components - multi-core processing elements (PEs), DRAM main memory systems, and on/off-chip interconnection networks - in multi-processor embedded systems are examined in each section respectively. The first section of this thesis presents architectural enhancements to graphics processing units (GPUs), one of the multi- or many-core PEs, for improving performance of embedded applications. An embedded application is first mapped onto GPUs to explore the design space, and then architectural enhancements to existing GPUs are proposed for improving throughput of the embedded application. The second section proposes high-performance buffer mapping methods, which exploit useful features of DRAM main memory systems, in DSP multi-processor systems. The memory wall problem becomes increasingly severe in multiprocessor environments because of communication and synchronization overheads. To alleviate the memory wall problem, this section exploits bank concurrency and page mode access of DRAM main memory systems for increasing the performance of multiprocessor DSP systems. The final section presents a network-centric Turbo decoder and network-centric FFT processors. In the era of multi-processor systems, an interconnection network is another performance bottleneck. To handle heavy communication traffic, this section applies a crossbar switch - one of the indirect networks - to the parallel Turbo decoder, and applies a mesh topology to the parallel FFT processors. When designing the mesh FFT processors, a very different approach is taken to improve performance; an optical fiber is used as a new interconnection medium.