Syftet med denna undersökning är att ta reda på hur den mobila marknadsföringen via SMS kan påverka köp och varumärkeslojaliteten hos konsumenterna, det vill säga återkommande köp samt om den leder till att lojaliteten till varumärket ökar på grund av detta. Vid undersökningen använde vi oss av en kvalitativ och en kvantitativ studie. Vi skickade ut enkäter till cirka 1500 personer via mail, dessa enkäter innehöll några frågor som det fanns svarsalternativ på medan de övriga av frågorna var öppna. Frågorna behandlade den mobila marknadsföringen via SMS där de fick svara på vad de tyckte om den, om det gjort något inköp efter att ha mottagit ett reklam-SMS och om de gjort återkommande inköp. De fick även svara på om de mottagit något positivt eller negativt reklam- SMS och vad som gjorde att det var detta. Svarsfrekvensen på enkäterna var dock låg med tanke på hur många som vi skickade ut den till. Det var 305 stycken som svarade på enkäten medan det endast var 230 stycken som svarade på hela enkäten. Då vi fick väldigt mycket svar på de öppna frågorna sammanställde vi empirin genom att i matriser komma fram till begrepp som ofta förekom i texten. Många tyckte att reklam-SMSet borde vara kort, intressant och innehålla ett bra erbjudande. På de stängda frågorna ska vi göra en statistisk analys för att se om ett samband finns. Det vi kom fram till vid denna studie, efter att ha analyserat teorin och empirin, var att det var ganska många som gjort inköp till följd av ett reklam-SMS men det var väldigt få som hade gjort återkommande inköp på grund av detta. Det var fler som aldrig hade gjort återkommande köp. Varumärket tog en större plats i medvetandet hos vissa men vi anser att den mobila marknadsföringen via SMS leder till att många konsumenter blir missnöjda då de tycker att det känns kränkande mot integriteten och irriterade att få reklam-SMS för ofta.

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There are three parts in this thesis: In the first part (Chapter 2), we discuss the port excitation (Wave port vs Lumped port) suitable for sub-millimeter wave operations. We realized on printed circuit board a grounded coplanar waveguide (CPWG) and on gallium arsenic (GaAs) a microstrip line. We performed simulation on these structures using high frequency structure simulator (HFSS), and compared the results with measured ones. From the comparison, we found close match for CPWG insertion loss from 10 MHz to 67 GHz using the Wave port. However, for G-S-G lumped port, only matched up to 40 GHz. The wave port not only was more accurate, but also consumed less time in simulation. Consequently, we employed wave port as our simulation excitation for our sub-millimeter wave QFN design. In the second part (Chapter 3), we focused on design of low cost QFN for sub-millimeter wave applications. We fabricated test structures, which include IC pads and transmission lines, wire bonds, QFN leads, and G-S-G structures on printed circuit board. In HFSS simulation, our specially designed ribbon bonds and QFN configuration show return loss less than -20dB and insertion loss less than -0.4 dB up to 60 GHz. Using the same design principles, we strived to improve the performance of a commercially available QFN, which normally operates at 3 to 6 GHz. The extraction method to obtain the high frequency characteristics was introduced first, and the characteristics of a commercially available QFN (with our wire bond configuration) were then obtained. The insertion loss was less than -20 dB and insertion loss less than -0.5 dB up to 20 GHz. In Chapter 5, we discuss the performance discrepancies between the simulated ribbon bond results and that for fabricated wire bonds. In the third part (Chapter 4), we introduced a method to extract the characteristics of a single backside via and investigated the effects of die attachment on the performance of a single and multiple backside via(s). Using silver epoxy and Cu blank layer as die attach methods, we found it was important to provide a broad path (Cu blank layer), as opposed to a restrict path (like silver epoxy) to reduce the inductance of the backside vias. The conclusion and future work are provided in Chapter 5.

In this thesis, we study the discontinuity structure electromagnetic effect of multilayer printed circuit board in three sections. In first section, we introduced a modeling approach which is based on transmission line theory , and simulated with a series of test boards ,such as regular and irregular power delivery system and multilayer with via structure, finally ,we confirmed that the modeling approach is an efficient simulation and agreed fairly well with 3D full-wave method. In second section, we demonstrated the return current is disrupted at the via or broken at the power / ground plane with slots , the impedance becomes extremely high at the resonance frequencies of the power / ground plane cavity and via could be a major cause of the simultaneous switching noise generation, signal quality problem, and edge radiated emission in multi-layer PCB. In final section, we provided a effective reduction mechanism to eliminate the noise or EMI, which has been achieved using island with shorting vias and combining with the modeling approach can simulate and estimate effectively.

The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.

Στην παρούσα διπλωματική εργασία γίνεται διερεύνηση των βέλτιστων τεχνικών παραμέτρων σχεδιασμού υβριδικής τηλεπικοινωνιακής πλατφόρμας για την υποστήριξη της υπηρεσίας DVB-H μέσω δορυφόρου. Γίνεται μοντελοποίηση των δύο τύπων μεταδόσεων, επίγειας και δορυφορικής. Τα αποτελέσματα που εξάγονται από τις προσομειώσεις συγκρίνονται με στοιχεία που καθορίζουν πρότυπα του ΕTSI. / In this thesis are worked out the optimised parameters for the design of an hybrid platform which supports the DVB-H (Digital Video Broadcasting for Handheld devices)service via satellite. Two kinds of broadcasting are modelled, terrestrial and satellite. The results of the simulation of these models are compared with elements which are defined by ETSI standards.

With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area respectively. These concerns have led to an effort to find a solution that would reduce interconnect delay and leakage, while also reducing the area they occupy in a chip, so that either the chip area could be reduced, or more functionality could be incorporated within a certain area. 3D integration, i.e., stacking of various sub-systems of a chip on top of each other, enables chip-makers to achieve higher packaging efficiencies, thereby reducing system cost, while also reducing delay (and thus increasing the available bandwidth). Through Silicon Vias (TSVs) have emerged as the key interconnect technology for 3D ICs, as they enable significant reduction in delay and leakage compared to wire-bonded dies, while also occupying less area in a package. They also enable stacking of sub-systems which differ in functionality, and stacking of multiple dies. Also, unlike wire-bond, dies need not be bandwidth limited by the number of wire bonds that can be made between two levels in a stack. While TSVs offer many advantages, one of the concerns when implementing a 3D system using TSVs is the mechanisms of interaction between a TSV and a device in its vicinity. Another concern is with regards to the interaction between the TSV and its surrounding material. The purpose of this thesis is to develop a TCAD framework for process and device co-simulation of a TSV transistor system to study the various mechanisms of interaction between them, as well as between the TSV and substrate. The utility of this tool has been demonstrated by studying two mechanisms of interaction, the effect of TSV-induced stress, and the effect of TSV-device electrical coupling, on the electrical performance of bulk NMOS and PMOS transistors. The results from 3D TCAD simulations suggest that designers can scale the keep out zone (KOZ) around TSVs more aggressively, allowing for more efficient utilization of silicon area, without a drastic performance penalty.

Differential interconnects are extensively used in high-speed digital circuits at fast data rates and in environments of high noise like backplanes. For such applications they are preferred over single-ended lines owing to their ability to reject common-mode noise. Differential schemes like Low Voltage Differential Signaling (LVDS) are used for wireless base stations and ATM switches in telecommunication applications, flat panel displays and servers and for system-level clock distribution. LVDS applications use data rates from 100 Mbps to about 1.5 Gbps and are expected to be highly immune to noise. However, noise will also be injected into differential signals at these high data rates, if there are irregularities in the interconnect setup. These anomalies may be via transitions from differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. The differential setup is expected to be immune to such imbalances; however, investigation of these discontinuities indicate that sufficient signal energy can be leaked to power distribution networks (PDN) of packages and boards. The effect of this energy loss was examined in time-domain and was found to cause signal integrity effects like jitter. Irregular differential structures were compared with the equivalent single-ended configuration and symmetrical perfect differential lines. This thesis work quantifies signal to power coupling caused by irregular differential structures in the presence of PDN planes in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The jitter induced as a result of signal to power coupling from differential lines was also investigated.

Diss. Umeå : Umeå universitet, 2008.

Thesis (Ph.D.)--George Mason University, 2009. / Vita: p. 117. Thesis director: Gary Galluzzo. Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Education. Title from PDF t.p. (viewed Oct. 11, 2009). Includes bibliographical references (p. 110-116). Also issued in print.