Les sols de montagne représentent d'importants réservoirs de carbone (C) potentiellement vulnérables aux changements climatiques et changements d'usage qui les affectent de manière amplifiée. Or la grande variabilité de ces milieux, leur faible accessibilité ainsi que le manque d'outils de mesure appropriés limitent nos connaissances qui restent aujourd'hui très fragmentaires en ce qui concerne les stocks, la chimie et la réactivité du carbone organique des sols (COS). Ces informations sont pourtant nécessaires pour appréhender l'évolution de ces sols et de leur C dans ce contexte de changements globaux. Les objectifs de ce travail de thèse étaient (i) d'accéder à une meilleure compréhension de la nature, de la stabilité et de la vulnérabilité du COS dans une mosaïque d'écosystèmes des Préalpes calcaires (massif du Vercors), (ii) de rechercher des outils de caractérisation rapides et fiables adaptés à l'étude et au suivi du COS à l'échelle du paysage, et enfin (iii) de proposer des indices pour l'évaluation et le suivi de la qualité des sols en milieu de montagne. Dans un premier temps, nous avons testé l'application de la pyrolyse Rock-Eval pour l'étude du COS à grande échelle sur un ensemble d'unités écosystémiques. Nous avons ensuite comparé la pyrolyse Rock-Eval à deux techniques classiques d'étude de la matière organique du sol (MOS) : le fractionnement granulodensimétrique de la MOS et la spectroscopie moyen infrarouge. Ces approches analytiques couplées nous ont permis de quantifier les stocks de C à l'échelle de la zone d'étude et d'expliquer la stabilité et la vulnérabilité du COS sous des angles variés. Les facteurs responsables des patrons observés dans les différentes unités écosystémiques sont discutés. Ce travail a également confirmé la pertinence de l'outil Rock-Eval pour répondre aux objectifs fixés. Parallèlement, des approches biologiques nous ont permis d'évaluer l'importance de la composante microbienne dans ces sols. Enfin, des indices évaluant le statut organique des sols (stockage de COS, fertilité des sols, vulnérabilité du COS) sont proposés pour constituer des outils de gestion et d'aide à la décision. / Mountain soils are major reservoirs of carbon (C), potentially vulnerable to climate and land use changes that affect them significantly. However, the great variability of these soils, their limited accessibility and the lack of appropriate measurement tools restrict our knowledge. Today, our comprehension of the biogeochemistry of mountain soils remains very incomplete regarding stocks, chemistry and reactivity of soil organic carbon (SOC). Yet this information is necessary to understand the evolution of soil carbon in the current context of global change. The objectives of this work were (i) to gain a better understanding of the nature, stability and vulnerability of SOC in a mosaic of ecosystems in a calcareous massif in the Alps (Vercors massif), (ii) to search for fast and reliable characterization tools, suitable for the study and monitoring of COS at the landscape scale, and (iii) to propose indicators for the assessment and monitoring of soil quality in mountain regions. As a first step, we tested the application of Rock-Eval pyrolysis for the study of COS at large-scale on a set of ecosystem units. Then, we compared the Rock-Eval approach to two conventional techniques for soil organic matter (SOM) study: the particle-size fractionation of SOM, and the mid-infrared spectroscopy. These coupled analytical approaches allowed us to quantify C stocks across the study area, and explain the stability and the vulnerability of COS at various angles. Factors responsible for the patterns observed in the different eco-units are discussed. This work also confirmed the relevance of the Rock-Eval tool to achieve our previous objectives. Biological approaches allowed us to assess the significance of microbial pool in these soils. Finally, indices assessing the status of SOM (SOC storage, soil fertility, vulnerability COS) were proposed and constituted interesting management tools for decision-makers.

System on Chip (SoC) and System in Package (SiP) are two electronic technologies that involve integrating multiple functionalities onto a single platform. When the platform is a single wafer, as in SOC, it requires the ability to deposit various materials that enable the different functions on to an underlying substrate that can host the electronic circuitry. Transition metal oxides which have a wide range of properties are ideal candidates for the functional material. Si wafer on which micro-electronics technology is widely commercialized is the ideal host platform. Integrating oxides with Si, generally in the form of thin films as required by microelectronics technology, is however a challenge. It starts with the fact that the properties of crystalline oxides to be exploited in performing various functions are direction dependent. Thus, thin films of these oxides need to be deposited on Si in certain crystallographic orientations. Even if a suitably oriented Si wafer surface were available, it does not always provide for epitaxial growth a critical requirement for controlling the crystalline orientation of thin films. This is because Si surface is covered by an amorphous oxide of Si (SiOx). Thus, during growth of the functional oxide, an ambience in which the Si itself will not oxidize needs to be provided. In addition, during thin film growth on either Si or SiOx surface stresses are generated from various sources. Stress and its relaxation are also associated with the formation and evolution of defects. Both, stress and defects need to be managed in order to harness their beneficial effects and prevent detrimental ones. Given the requirement of SoC technology and the problem associated, the research work reported in this thesis was hence concerned with the precise controlling the stress and microstructure in oxide thin films deposited on Si substrates. In order to do so a versatile, ultra high vacuum (UHV) thin film with a base pressure of 10-9 Torr was designed and built as part of this study. The chamber is capable of depositing films by both sputtering (RF & DC) and pulsed laser ablation (PLD). The system has been designed to include an optical curvature measurement tool that enabled real-time stress measurement during growth. Doped zirconia, ZrO2, was chosen as the first oxide to be deposited, as it is among the few oxides that is more stable than SiOx. It is hence used as a buffer layer. It is shown in this thesis that a change in the growth rate at nucleation can lead to (100) or (111) textured films. These two are among the most commonly preferred orientation. Following nucleation a change in growth rate does not affect orientation but affects stress. Thus, independent selection of texture and stress is demonstrated in YSZ thin films on Si. A quantitative model based on the adatom motion on the growth surface and the anisotropic growth rates of the two orientations is used to explain these observations. This study was then subsequent extended to the growth on platinized Si another commonly used Si platform.. A knowledge of the stress and microstructure tailoring in cubic zirconia on Si was then extended to look at the effect of stress on electrical properties of zirconia on germanium for high-k dielectric applications. Ge channels are expected to play a key role in next generation n-MOS technology. Development of high-k dielectrics for channel control is hence essential. Interesting stress and property relations were analyzed in ZrO2/Ge. Stress and texture in pulsed laser deposited (PLD) oxides on silicon and SrTiO3 were studied. It is shown in this thesis that stress tuning is critical to achieve the highest possible dielectric constant. The effect of stress on dielectric constant is due to two reasons. The first one is an indirect effect involving the effect of stress on phase stability. The second one is the direct effect involving interatomic distance. By stress control an equivalent oxide thickness (EOT) of 0.8 nm was achieved in sputter deposited ZrO2/Ge films at 5 nm thickness. This is among the best reported till date. Finally, the effect of growth parameters and deposition geometry on the microstructural and stress evolution during deposition of SrTiO3 on Si and BaTiO3 on SrTiO3 by pulsed laser deposition is the same chamber is described.

Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traffic representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-off study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.

Network on Chip is a scalable and flexible communication infrastructure for the design of core based System on Chip. Communication performance of a NoC depends heavily on the routing algorithm. Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. In this thesis we make a case for the use of source routing for NoCs, especially for regular topologies like mesh. The advantages of source routing include in-order packet delivery; faster and simpler router design; and possibility of mixing non-minimal paths in a mainly minimal routing. We propose a method to compute paths for various communications in such a way that traffic congestion is avoided while ensuring deadlock free routing. We also propose an efficient scheme to encode the paths. We developed a tool in Matlab that computes paths for source routing for both general and application specific communications. Depending upon the type of traffic, this tool computes paths for source routing by selecting best routing algorithm out of many routing algorithms. The tool uses a constructive path improvement algorithm to compute paths that give more uniform link load distribution. It also generates different types of traffics. We also developed a simulator capable of simulating source routing for mesh topology NoC. The experiments and simulations which we performed were successful and the results show that the advantages of source routing especially lower packet latency more than compensate its disadvantages. The results also demonstrate that source routing can be a good routing candidate for practical core based SoCs design using network on chip communication infrastructure.

In addition to the performance, low power design became an important issue in the design process of mobile embedded systems. Mobile electronics with rich features most often involve complex computation and intensive processing, which result in short battery lifetime and particularly when low power design is not taken in consideration. In addition to mobile computers, thermal design is also calling for low power techniques to avoid components overheat especially with VLSI technology. Low power design has traced a new era. In this thesis we examined several techniques to achieve low power design for FPGAs, ASICs and Processors where ASICs were more flexible to exploit the HW oriented techniques for low power consumption. We surveyed several power estimation methodologies where all of them were prone to at least one disadvantage. We also compared and analyzed the power and energy consumption in three different designs, which perform matrix multiplication within Altera platform and using state-of-the-art FPGA device. We concluded that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multipliers on FPGAs and configware is an enormous potential to reduce the energy consumption costs.

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.

Lead acid batteries are widely used in domestic, industrial and automotive applications. Even after lot of advancements in battery technologies, lead acid cells are still in use because of their high capacity and low cost. To use any battery effectively, first we should be able to identify the available capacity or State of Charge (SoC). There are many techniques available to measure SoC of a lead acid battery. One such unique method is to measure the capacity using eddy current sensors. This method is unique because it is non-obtrusive and online. Eddy current sensors (ECS) are wire wound inductors which work on the principle of electromagnetic induction. Eddy currents are the currents generated on a conductive material when it is kept in a varying magnetic. Eddy current sensors generate varying magnetic eldest and will be able to identify the properties of conductive materials like thickness, conductivity, material composition etc. Also they can be used as proximity sensors. Lead acid batteries use lead metal as cathode. Upon usage(discharge) the lead metal converts to lead sulfate and revert back to lead after charging. These changes in lead electrode can be monitored using eddy current sensors. The impedance of an eddy current sensor will change when it is kept close to the lead electrode when the battery is charging or discharging. These impedance parameters can be monitored to determine the battery SoC. When lead is deposited on cathode, there will be more eddy current loss in the target and the total resistance of coil increases. On the other hand, when lead is deposited on the electrode because of increase in the magnitude of eddy currents which oppose the source magnetic, the total inductance of coil decreases. We can observe exactly opposite behaviour of coil resistance and inductance when the lead electrode is converted to less conductive lead sulfate. There is a lot of research on using ECS to measure SoC of lead acid batteries and there are still many challenges to be addressed. First we have explained about different circuit designs we have used to monitor the battery capacity using eddy current sensors. After that, we have explained about our complete experimental setup and the procedure to measure the sensor parameters using the setup. Then, we have discussed about different issues involved in the eddy current sensing based state of charge measurement. Eddy current sensors are affected by temperature variations. We have studied the coil resistance behaviour with temperature at different frequencies using simulations and experiments. We have obtained the conditions for linear variation of coil resistance with temperature. The measured temperature compensation scheme is applied and the results are discussed. We have also modified the measurement system design in order to minimize the lift o errors. We have used a metallic clamp structure to minimize the lift o errors. We have used finite element analysis based simulations to study different design parameters and their effect on the sensitivity of eddy current sensor. We have created 2D eddy current models and the sensitivity of coil resistance is computed by changing the coil dimensions and the core permeability. We have also performed error analysis and computed the error due to the tilt angle shift between coil and electrode. We have also computed the error due to the internal heating of battery. We have also studied the effect of acid strati cation on state of charge for both sealed and hooded batteries. We have proposed a multi coil method to minimize the errors in SoC measurement due to acid strati cation for Flooded type batteries. We have used finite element analysis based simulations to compute the error due to acid strati cation by increasing the number of coils. Finally we have derived the equation for electrode Q factor using the transformer model of eddy current sensor. The derived Q factor equation is then used to study the aging of lead acid batteries both by using experiments and simulations. Finally we have explained a detail procedure to measure the state of charge(SoC) and state of health(SoH) of a hooded lead acid battery using eddy current sensing method.

Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the transistor count is as large as billions of gate for some of the microprocessors. The design complexity is further projected to increase in the coming years in accordance with Moore's law. The larger gate count and integration of multiple functionalities are the causes for higher test power dissipation, test time and data volume. The dynamic power dissipation during scan testing, i.e. during scan shift, launch and response capture, are major concerns for reliable as well as cost effective testing. Excessive average power dissipation leads to a thermal problem which causes burn-out of the chip during testing. Peak power on other hand causes test failure due to power induced additional delay. The test failure has direct impact on yield. The test power problem in modern 3D stacked based IC is even a more serious issue. Estimating the worst case functional power dissipation is yet another great challenge. The worst case functional power estimation is necessary because it gives an upper bound on the functional power dissipation which can further be used to determine the safe power zone for the test. Several solutions in the past have been proposed to address these issues. In this thesis we have three major contributions: 1) Sequential scan chain reordering, and 2) JScan-an alternative Joint-scan DFT architecture to address primarily the test power issues along with test time and data volume, and 3) an integer linear programming methodology to address the power estimation problem. In order to reduce test power during shift, we have proposed a graph theoretic formulation for scan chain reordering and for optimum scan shift operation. For each formulation a set of algorithms is proposed. The experimental results on ISCAS-89 benchmark circuit show a reduction of around 25% and 15% in peak power and scan shift time respectively. In order to have a holistic DFT architecture which could solve test power, test time, and data volume problems, a new DFT architecture called Joint-scan (JScan) have been developed. In JScan we have integrated the serial and random access scan architectures in a systematic way by which the JScan could harness the respective advantages from each of the architectures. The serial scan architecture from test power, test time, and data volume problems. However, the serial scan is simple in terms of its functionality and is cost effective in terms of DFT circuitry. Whereas, the random ac-cess scan architecture is opposite to this; it is power efficient and it takes lesser time and data volume compared to serial scan. However, the random access scan occupies larger DFT area and introduces routing congestion. Therefore, we have proposed a methodology to realize the JScan architecture as an efficient alternative for standard serial and random access scan. Further, the JScan architecture is optimized and it resulted into a 2-Mode 2M-Jscan Joint-scan architecture. The proposed architectures are experimentally verified on larger benchmark circuits and compared with existing state of the art DFT architectures. The results show a reduction of 50% to 80% in test power and 30% to 50% in test time and data volume. The proposed architectures are also evaluated for routing area minimization and we obtained a saving of around 7% to 15% of chip area. Estimating the worst case functional power being a challenging problem, we have proposed a binary integer linear programming (BILP) based methodology. Two different formulations have been proposed considering the different delay models namely zero-delay and unit-delay. The proposed methodology generates a pair or input vectors which could toggle the circuit to dissipate worst power. The BILP problems are solved using CPLEX solver for ISCAS-85 combinational benchmark circuits. For some of the circuits, the proposed methodology provided the worst possible power dissipation i.e. 80 to 100% toggling in nets.

<p>Minimum cycle mean (MCM) is an important concept in directed graphs. From clock period optimization, timing analysis to layout optimization, minimum cycle mean algorithms have found widespread use in VLSI system design optimization. With transistor size scaling to 10nm and below, complexities and size of the systems have grown rapidly over the last decade. Scalability of the algorithms both in terms of their runtime and memory usage is therefore important. </p> <p><br></p> <p>Among the few classical MCM algorithms, the algorithm by Young, Tarjan, and Orlin (YTO), has been particularly popular. When implemented with a binary heap, the YTO algorithm has the best runtime performance although it has higher asymptotic time complexity than Karp's algorithm. However, as an efficient implementation of YTO relies on data redundancy, its memory usage is higher and could be a prohibitive factor in large size problems. On the other hand, a typical implementation of Karp's algorithm can also be memory hungry. An early termination technique from Hartmann and Orlin (HO) can be directly applied to Karp's algorithm to improve its runtime performance and memory usage. Although not as efficient as YTO in runtime, HO algorithm has much less memory usage than YTO. We propose several improvements to HO algorithm. The proposed algorithm has comparable runtime performance to YTO for circuit graphs and dense random graphs while being better than HO algorithm in memory usage. </p> <p><br></p> <p>Minimum balancing of a directed graph is an application of the minimum cycle mean algorithm. Minimum balance algorithms have been used to optimally distribute slack for mitigating process variation induced timing violation issues in clock network. In a conventional minimum balance algorithm, the principal subroutine is that of finding MCM in a graph. In particular, the minimum balance algorithm iteratively finds the minimum cycle mean and the corresponding minimum-mean cycle, and uses the mean and cycle to update the graph by changing edge weights and reducing the graph size. The iterations terminate when the updated graph is a single node. Studies have shown that the bottleneck of the iterative process is the graph update operation as previous approaches involved updating the entire graph. We propose an improvement to the minimum balance algorithm by performing fewer changes to the edge weights in each iteration, resulting in better efficiency.</p> <p><br></p> <p>We also apply the minimum cycle mean algorithm in latency insensitive system design. Timing violations can occur in high performance communication links in system-on-chips (SoCs) in the late stages of the physical design process. To address the issues, latency insensitive systems (LISs) employ pipelining in the communication channels through insertion of the relay stations. Although the functionality of a LIS is robust with respect to the communication latencies, such insertion can degrade system throughput performance. Earlier studies have shown that the proper sizing of buffer queues after relay station insertion could eliminate such performance loss. However, solving the problem of maximum performance buffer queue sizing requires use of mixed integer linear programming (MILP) of which runtime is not scalable. We formulate the problem as a parameterized graph optimization problem where for every communication channel there is a parameterized edge with buffer counts as the edge weight. We then use minimum cycle mean algorithm to determine from which edges buffers can be removed safely without creating negative cycles. This is done iteratively in the similar style as the minimum balance algorithm. Experimental results suggest that the proposed approach is scalable. Moreover, quality of the solution is observed to be as good as that of the MILP based approach.</p><p><br></p>

Les médias sociaux et les sites de réseaux sociaux sont devenus des babillards numériques pour les internautes à cause de leur évolution accélérée. Comme ces sites encouragent les consommateurs à exposer des informations personnelles via des profils et des publications, l'utilisation accrue des médias sociaux a généré des problèmes d’invasion de la vie privée. Des chercheurs ont fait de nombreux efforts pour détecter l'auto-divulgation en utilisant des techniques d'extraction d'informations. Des recherches récentes sur l'apprentissage automatique et les méthodes de traitement du langage naturel montrent que la compréhension du sens contextuel des mots peut entraîner une meilleure précision que les méthodes d'extraction de données traditionnelles. Comme mentionné précédemment, les utilisateurs ignorent souvent la quantité d'informations personnelles publiées dans les forums en ligne. Il est donc nécessaire de détecter les diverses divulgations en langage naturel et de leur donner le choix de tester la possibilité de divulgation avant de publier. Pour ce faire, ce travail propose le « SD_ELECTRA », un modèle de langage spécifique au contexte. Ce type de modèle détecte les divulgations d'intérêts, de données personnelles, d'éducation et de travail, de relations, de personnalité, de résidence, de voyage et d'accueil dans les données des médias sociaux. L'objectif est de créer un modèle linguistique spécifique au contexte sur une plate-forme de médias sociaux qui fonctionne mieux que les modèles linguistiques généraux. De plus, les récents progrès des modèles de transformateurs ont ouvert la voie à la formation de modèles de langage à partir de zéro et à des scores plus élevés. Les résultats expérimentaux montrent que SD_ELECTRA a surpassé le modèle de base dans toutes les métriques considérées pour la méthode de classification de texte standard. En outre, les résultats montrent également que l'entraînement d'un modèle de langage avec un corpus spécifique au contexte de préentraînement plus petit sur un seul GPU peut améliorer les performances. Une application Web illustrative est conçue pour permettre aux utilisateurs de tester les possibilités de divulgation dans leurs publications sur les réseaux sociaux. En conséquence, en utilisant l'efficacité du modèle suggéré, les utilisateurs pourraient obtenir un apprentissage en temps réel sur l'auto-divulgation. / Social media and social networking sites have evolved into digital billboards for internet users due to their rapid expansion. As these sites encourage consumers to expose personal information via profiles and postings, increased use of social media has generated privacy concerns. There have been notable efforts from researchers to detect self-disclosure using Information extraction (IE) techniques. Recent research on machine learning and natural language processing methods shows that understanding the contextual meaning of the words can result in better accuracy than traditional data extraction methods. Driven by the facts mentioned earlier, users are often ignorant of the quantity of personal information published in online forums, there is a need to detect various disclosures in natural language and give them a choice to test the possibility of disclosure before posting. For this purpose, this work proposes "SD_ELECTRA," a context-specific language model to detect Interest, Personal, Education and Work, Relationship, Personality, Residence, Travel plan, and Hospitality disclosures in social media data. The goal is to create a context-specific language model on a social media platform that performs better than the general language models. Moreover, recent advancements in transformer models paved the way to train language models from scratch and achieve higher scores. Experimental results show that SD_ELECTRA has outperformed the base model in all considered metrics for the standard text classification method. In addition, the results also show that training a language model with a smaller pre-training context-specific corpus on a single GPU can improve its performance. An illustrative web application designed allows users to test the disclosure possibilities in their social media posts. As a result, by utilizing the efficiency of the suggested model, users would be able to get real-time learning on self-disclosure.