Abstract In this thesis, we propose and fabricate a triple recessed multi-gate SOI device that has high transconductance and low series resistance. The SOI device structure has three unique features. First, it uses mesa isolation instead of using conventional LOCOS and trench isolation to avoid the bird¡¦s beak effect in LOCOS isolation and the complexity of digging trench in trench isolation. Second, it combines the rounded and gate recessed structure to reduce the edge effect and lower the source/drain parasitic resistance. Third, it has three surfaces of gate structure that can increase the effective channel width of the device to enhance the current drivability of the device without reducing the packing density of the integrated circuit. From our experiment results the trends of device characteristics exhibits good agreement with the 3 ¡V D simulation results. According to the simulation results of 3 ¡V D DAVINCI and the measurement results, triple recessed multi-gate SOI MOSFET¡¦s presents four unique characteristics, which are superior to conventional SOI with the same device parameter in deep sub-micrometer regime. First, multi-gate SOI has better short channel effect and drain induce barrier lowing immunity conventional SOI device than conventional SOI device. Second, it has higher transconductance and higher current drive capability. Third, the breakdown voltage is higher than that of conventional SOI device. Fourth, self-heating effect would not increase with current gain increase, triple recessed multi-gate SOI device has better self-heating effect immunity. These four advantages show the triple recessed multi-gate SOI MOSFET¡¦s is suitable for high speed and low power applications along shrink of device dimensions.

Abstract The tendency to manufacture of semiconductor is to minimize the size of device. With the size was minimized, the number of transistor on the chip was maximized at the same time .However, when the drift region of Power-MOSFET is shorter will result in the Breakdown Voltage is lower, so this do not conform our purpose for application, and therefore we should look for some alternative method to enhance efficiency. One of these method of efficiency promotion is adopting channel strain. We adopt bending silicon substrate to obtain strain. By using this method, we successfully enhance drain current and mobility 12.1% and 4.1% individually. Furthermore, regarding the reliability study, we realize the hot-carrier effect influence under strain silicon. The longer the size(Lg & DL) of Power- MOSFET , the reliability is better. When device were bent under Bending R=40mm and Lg=0.8(m conditions, we can obtain the better reliability of device than flat chip.

For many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs). / text

Introducing the notion of transformational silicon electronics has paved the way for integrating various applications with silicon-based, modern, high-performance electronic circuits that are mechanically flexible and optically semitransparent. While maintaining large-scale production and prototyping rapidity, this flexible and translucent scheme demonstrates the potential to transform conventionally stiff electronic devices into thin and foldable ones without compromising long-term performance and reliability. In this work, we report on the fabrication and characterization of reversibly bistable flexible electronic switches that utilize flexible n-channel metal-oxide-semiconductor field-effect transistors. The transistors are fabricated initially on rigid (100) silicon substrates before they are peeled off. They can be used to control flexible batches of light-emitting diodes, demonstrating both the relative ease of scaling at minimum cost and maximum reliability and the feasibility of integration. The peeled-off silicon fabric is about 25 µm thick. The fabricated devices are transferred to a reversibly bistable flexible platform through which, for example, a flexible smartphone can be wrapped around a user’s wrist and can also be set back to its original mechanical position. Buckling and cyclic bending of such host platforms brings a completely new dimension to the development of flexible electronics, especially rollable displays.

This thesis develops a hardware circuit implementation of an active filter for reducing a SRM drives input current ripple or equivalently to improve the SRM drives input power quality. Its an alternative to the simple inductor and capacitor in a conventional passive filter. For the same filtering capability the size of the two physical capacitors in the active filter will be much less than the size of the capacitor in a conventional filter. Also the size of the two inductors in the active filter will be much less than the size of the inductor in a conventional filter. Some of this size reduction will be consumed by the power semiconductors but their size is much smaller than the filter components being replaced. This thesis describes the design of the active filter circuit which can replace the conventional passive filter. In this thesis, feedback control is also used with the active filter to force the filter voltage to be the desired value to minimize the effects of the circuits resonances. The active filter circuit is tested experimentally with a test circuit that mimics the current ripple generated by an SRM drive system. The experimentally generated output is verified by comparing it with simulation results from a detailed SIMULINK model and a B2 spice model of the experimental system.

Det här arbetet handlar om designa ett effektelektronikkort till National Instruments utvecklingsplattform ELVIS II, som skakunna styras från programmet LabVIEW. Kortet är tänkt att kunna användas i kurser inom effektelektronik på högskolenivåoch har designats för att passa ELVIS II's hårdvaruspecifikationer. I arbetet har alla kretsar byggts upp och simulerats iMultisim. Kretsarna som designats är en step-up-konverterare, en step-down-konverterare, en likriktare, en växelriktare ochen variabel last. Simuleringarna visade att kretsarna fungerar som tänkt och vad som skiljer sig från det teoretiska. Någotsom ofta visade sig i simuleringarna var att strömförbrukningen under korta perioder kraftigt kan överstiga det ELVIS II kanleverera, vilket behöver undersökas närmare. Rapporten innehåller scheman och simuleringsresultat från alla kretsar, vadsom är kvar att lösa på dessa och hur dessa kan anslutas till ELVIS II.

Submitted by Isaac Francisco de Souza Dias (isaac.souzadias@ufpe.br) on 2016-01-19T18:10:45Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) Lenon Mendes Dissertacao Mestrado 2015.pdf: 3797605 bytes, checksum: 7022202de7a4af31595ea4374ab76da7 (MD5) / Made available in DSpace on 2016-01-19T18:10:45Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) Lenon Mendes Dissertacao Mestrado 2015.pdf: 3797605 bytes, checksum: 7022202de7a4af31595ea4374ab76da7 (MD5) Previous issue date: 2015-05-29 / CAPES / Este trabalho visa caracterizar o MOSkin para dosimetria em tomografia computadorizada. Desta forma, a resposta do detector foi avaliada para as qualidades de referência RQT 8, RQT 9 e RQT 10 e estudos foram realizados para avaliar a sensibilidade, dependência energética, reprodutibilidade, desvanecimento e dependência angular da resposta do dosímetro. Em seguida, o dosímetro foi empregado para avaliação do kerma ar em um tomógrafo Philips Brilliance 6 CT e o seu desempenho foi comparado com o filme radiocrômico Gafchromic XR-CT, dosímetros termoluminescentes TLD-100 e uma câmara de ionização tipo lápis. Os resultados mostraram que a resposta do dosímetro é linear e reprodutível dentro da faixa de dose escolhida (até 7 cGy). Para as energias de feixe avaliadas, o fator de correção para a dependência energética variou no máximo 15% e a dependência angular foi inferior à 7,78% na faixa de 0 a 90º. Assim como esperado, a sensibilidade do dosímetro declinou com o histórico de dose. Para um MOSkin irradiado com a qualidade de feixe RQT 9 (120 kV) a sensibilidade no final da vida útil era 4,76% menor do que a sensibilidade inicial. Porém, com o uso do processo de annealing por pulsos de corrente, foi possível recuperar a resposta do MOSkin, tornando-o reutilizável. Por fim, os resultados obtidos no tomógrafo mostraram que o MOSkin é adequado para obtenção da distribuição do kerma no ar em tomografia computadorizada e para a avaliação da Dose Total Acumulada no Centro. / The aim of this research was to characterize the response of the MOSkin dosimeter for x-ray Computed Tomography beams. The dosimeter’s response was evaluated for standard radiation qualities RQT 8, RQT 9 and RQT 10 and experiments were performed to investigate the sensitivity, energy dependence, reproducibility, fading and angular dependence of the response for the device. The MOSkin was also used for kerma air evaluation in a Philips Brilliance 6 CT unit and a comparison was made with TLD-100 thermoluminescents dosimeters, a radiochromic film Gafchromic XR-CT and a pencil ionization chamber. The results have shown that the MOSkin response was linear and reproducible within the kerma air range used in this research (until 7cGy). Energy dependence correction factors varied up to 15% among the tested x-ray energies. Angular dependence of the dosimeter was not greater than 7.78% within the angle range from 0 to 90 degrees. As expected, the MOSkin sensitivity was found to decline with the dose history. For a MOSkin irradiated at a tube potential of 120 kVp (RQT 9) the sensitivity at its end live was 4.76% smaller than the sensitivity at the beginning of its lifetime. Also, pulsed current annealing was proved to be successful for recovering the threshold voltage and sensitivity. At last, the MOSkin is proved a good alternative for the CT air kerma profile measurements and was adequate for the Total Accumulated Dose assessment.

No description available.

<p> The static electrical characteristics of dual-gate silicon n-channel insulated-gate field-effect trapsistors are investigated experimentally. A mathematical model based on theoretical expressions and containing twelve parameters adjusted for. best fit was developed. </p> <p> The mathematical model was used to calculate the low frequency conversion transconductance as a function of operating conditions. </p> / Thesis / Master of Engineering (MEngr)

Evolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance. Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits. Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance. / Ph. D.