Dans cette thèse, les propriétés électriques de transistors à nanofils de silicium liées à l'interface oxyde de grille/canal ont été étudiées par le biais de mesures de bruit basse fréquence (bruit 1/f) et de transport dans le canal. Ces transistors nanofils dont les dimensions ont été réduites jusqu'à quelques nanomètres pour la section, représentent une alternative sérieuse pour les futurs nœuds technologiques CMOS. Cependant, la qualité de l'interface oxyde de grille/canal pose question pour transistors dont l'architecture s'étend dans les 3 dimensions, en raison du fort rapport surface/volume inhérent à ces transistors, des différentes orientations cristallographiques de ces interfaces, ou encore des matériaux contraints utilisés pour améliorer les performances électriques. La compréhension des liens entre les propriétés de transport des porteurs dans le canal, qui garantissent en grande partie les performances électriques des transistors, et la qualité de l'interface avec l'oxyde de grille est fond primordiale pour optimiser les transistors nanofils. Les mesures de bruit, associées à l'étude du transport dans le canal, sont un outil puissant et adapté à ces dispositifs tridimensionnels, sans être limité par la taille ultra-réduite des transistors nanofils. Les transistors nanofils étudiés ont été fabriqués à partir de substrats minces SOI, et intègrent un empilement de grille HfSiON/TiN, qui permet de réduire les dimensions tout en conservant les mêmes propriétés électrostatiques. Pour gagner en performances, des contraintes mécaniques ont été introduites dans le canal en silicium : en tension pour les NMOS, par le biais de substrat contraint (sSOI), et en compression pour les PMOS. Un canal en compression uni-axiale peut être obtenu par l'intégration de source/drain en SiGe et/ou par l'utilisation de couches contraintes de type CESL. Des transistors à canal SiGe sur isolant en compression ont également été fabriqués et étudiés. Les caractéristiques électriques des divers transistors nanofils (courbes Id-Vg, compromis Ion-Ioff, mobilité des porteurs) démontrent l'excellent contrôle électrostatique dû à l'architecture 3D, ainsi que l'efficacité de l'ingénierie de contraintes dans les nanofils jusqu'à de faibles longueurs de grilles (~17nm). Des mesures de bruit basse fréquence ont été réalisées sur ces mêmes dispositifs et analysées en fonction des paramètres géométriques de l'architecture nanofils (largeur W, forme de la section, longueur de grille L), et des diverses variantes technologiques. Nous avons démontré que le bruit 1/f dans les transistors nanofils peut être décrit par le modèle de fluctuations du nombre de porteurs (CNF) corrélées aux fluctuations de mobilité (CMF). Le bruit associé aux régions S/D a pu également être intégré dans ce modèle en ajoutant une contribution, en particulier pour les PMOS. Alors que les différentes variantes technologiques ont peu d'effet sur le bruit 1/f, les variations de géométrie en L et W changent la composante de bruit liée aux fluctuations du nombre de porteurs (CNF) de manière inversement proportionnelle à la surface totale (~1/WL). Cette augmentation du bruit est le reflet du transport qui se produit à proximité des interfaces avec l'oxyde. Les différentes orientations des interfaces supérieures et latérales (110) ou (100) présentent la même quantité de pièges d'interface (extrait à partir des mesures de bruit 1/f, en séparant les contributions des différentes faces du nanofil) bien qu'ayant une rugosité différente essentiellement liée au process. En revanche la composante CMF n'est pas altérée par la réduction des dimensions contrairement à la mobilité des porteurs qui décroit fortement avec L. Finalement, les mesures de bruit 1/f ont été comparées aux spécifications ITRS 2013 pour les transistors multi-grilles en vue des futurs nœuds technologiques de la logique CMOS, et démontrent que nos transistors nanofils satisfont les exigences en la matière. / In this thesis, electrical properties of gate oxide/channel interface in ultra-scaled nanowire (NW) MOSFETs were experimentally investigated by carrier transport and low-frequency noise (LFN) characterizations. NW FETs, which have aggressively downscaled cross-section of the body, are strong candidates for near future CMOS node. However, the interface quality could be a critical issue due to the large surface/volume ratio, the multiple surface orientations, and additional strain technology to enhance the performance. Understanding of carrier transport and channel interface quality in NW FETs with advanced high-k/metal gate is thus particularly important. LFN provides deep insights into the interface properties of MOSFET without lower limit of required channel size. LFN measurement thus can be a powerful technique for ultra-scaled NW FETs. Also, fitting mobility (such as low-field mobility) extraction by Y-function method is an efficient method. Omega-gate NW FETs were fabricated from FD-SOI substrates, and with Hf-based high-k/metal gate (HfSiON/TiN), reducing detrimental effects by device downscaling. In addition, strain technologies to the channel were additively processed. Tensile strained-SOI substrate was used for NMOS, whereas compressive stressors were used for PMOS devices. Strained Si channel for PMOS was processed by raised SiGe S/D and CESL formations. Strained SiGe channel (SGOI) was also fabricated for further high-performance PMOS FETs. Firstly, the most common Id-Vg was characterized in single-channel NW FETs as the basic performance. Reference SOI NWs provided the excellent static control down to short channel of 17nm. Stressors dramatically enhanced on-current owing to a modification of channel energy-band structure. Then, extracted low-field mobility in NWs also showed large improvement of the performance by stressors. The mobility extraction effectively evaluated FET performance even for ultra-scaled NWs. Next, LFN investigated for various technological and architectural parameters. Carrier number fluctuations with correlated mobility fluctuations (CNF+CMF) model described 1/f noise in all our FETs down to the shortest NWs. Drain current noise behavior was basically similar in both N- and PMOS FETs regardless of technological splits. Larger 1/f noise stemming from S/D regions in PMOS FETs was perfectly interpreted by the CNF+CMF model completed with Rsd fluctuations. This observation highlighted an advantage of SGOI NW with the lowest level of S/D region noise. Geometrical variations altered the CNF component with simple impact of device scaling (reciprocal to both Wtot and Lg). No large impact of surface orientation difference between the channel (100) top and (110) side-walls in [110]-oriented NWs was observed. Scaling regularity with both Wtot and Lg, without much quantum effect, could be attributed to the use of HfSiON/TiN gate and carrier transport occurring mostly near top and side-wall surfaces even in NW geometry. Meanwhile, the CMF factor was not altered by decreasing dimensions, while the mobility strongly depends on the impact. Extracted oxide trap density was roughly steady with scaling, structure, and technological parameter impacts. Simple separation method of the contributions between channel top surface and side-walls was demonstrated in order to evaluate the difference. It revealed that oxide quality on (100) top and (110) side-walls was roughly comparable in all the [110]-devices. The density values lie in similar order as the recent reports. An excellent quality of the interface with HfSiON/TiN gate was thus sustained for all our technological and geometrical splits. Finally, our NWs fulfilled 1/f LFN requirements stated in the ITRS 2013 for future MG CMOS logic node. Consequently, we concluded that appropriate strain technologies powerfully improve both carrier transport and LFN property for future CMOS circuits consisting of NW FETs, without any large concern about the interface quality.

Em decorrência da necessidade de se obter circuitos integrados (CIs) cada vez mais velozes e consequentemente dando sequência à lei de Moore, a redução das dimensões dos dispositivos se torna necessária, aumentando assim a capacidade de integração de transistores dentro de um CI, porém, ao passo que ocorre a miniaturização, aparecem efeitos parasitários que afetam o comportamento dos transistores. Sendo assim, torna-se necessária a utilização de novos dispositivos e o uso de diferentes materiais, para dar continuidade à evolução tecnológica. Com o avanço da tecnologia, as indústrias seguiram em dois caminhos diferentes, a tecnologia planar (exemplo: UTBB) e a tridimensional (exemplo: FinFET). Neste trabalho são abordadas estas duas diferentes geometrias. Foram analisados dispositivos UTBOX e UTBB (planares) e os nanofios de porta ômega (?-Gate NW), que tem estrutura tridimensional. O uso de dispositivos com baixa-potência e baixa-tensão tornaram-se ainda mais importante nos dias de hoje, com aplicações em áreas médicas, como aparelhos auditivos e marca passos, em relógios inteligentes, microsensores e etc. Quanto menor for a potência consumida, menor será o calor gerado, resultando em uma redução de custos com sistemas de refrigeração. Os circuitos que operam na região de sublimiar são utilizados em aplicações onde o consumo de energia é mais importante do que a performance, porém, ao trabalhar nessa região os transistores apresentam um alto ganho para pouca variação de tensão. Nos transistores UTBOX e UTBB SOI nMOSFETs foram analisados os parâmetros partindo-se da tensão de limiar em direção à região do transistor no estado desligado, analisando a influência da espessura da região ativa do silício, do comprimento do canal e da implantação do plano de terra nos seguintes parâmetros: tensão de limiar, inclinação de sublimiar, abaixamento da barreira induzido pelo dreno (DIBL), a fuga no dreno induzida pela porta (GIDL) e razão das correntes no estado ligado e desligado (ION/IOFF). A redução do comprimento de canal afeta todos os parâmetros, devido ao efeito de canal curto, que além de reduzir a tensão de limiar, quando o dispositivo opera com baixo VDS (tensão entre dreno (VD) e fonte (VS)), reduz ainda mais quando aplicado alto VDS (em saturação), aumentando o DIBL. Esse efeito foi observado para os dispositivos nanofios com porta ômega, nos três valores de largura de canal analisados. Com o VDS alto também ocorre mais fuga de corrente pela segunda interface para comprimentos de canal curto, o que reduz a razão ION/IOFF. Quanto mais fina é a espessura do canal, melhor é o acoplamento entre as interfaces, resultando em uma melhor inclinação de sublimiar (SS) tornando os valores próximos ao limite teórico de 60mV/dec à temperatura ambiente. Nos resultados experimentais foi possível observar, para os dispositivos UTBOX e UTBB, uma redução de SS de aproximadamente 20 mV/dec, com a redução de tsi. A espessura da região ativa do silício também influencia na distribuição do campo elétrico, sendo diretamente proporcional, ou seja, quanto mais espessa a camada de silício, maior será o campo elétrico. A implantação do plano de terra (GP) tem como um de seus objetivos reduzir as cargas de depleção que são formadas abaixo do óxido enterrado e assim melhorar o controle das cargas no canal pela tensão aplicada no substrato. Essas cargas de depleção aumentam a espessura efetiva do óxido enterrado e também influenciam as cargas dentro do canal, resultando em um maior potencial na segunda interface (canal/óxido enterrado), facilitando a condução no canal, ou seja, reduzindo o valor de VT. Com a presença do GP, o potencial na segunda interface é mais próximo de zero, o que reduz a condução por essa região. Com isso será necessária uma maior tensão para inverter o canal. Porém, o controle das cargas pela tensão aplicada na porta é maior. Os valores extraídos de VT sem GP foram de aproximadamente 0,25V e com GP aproximadamente 0,45V. O estudo feito nos transistores de estrutura de nanofio e porta ômega NMOS e PMOS foi baseado em três parâmetros: tensão de limiar, inclinação de sublimiar e DIBL, com diferentes comprimentos e larguras de canal, sendo possível observar a presença do efeito de canal curto ao analisar os três parâmetros para L a partir de 100nm. Os transistores com Wfin=220nm apresentaram um menor VT em relação aos demais, para explorar esse fato, foram feitas simulações numéricas dos transistores do tipo N com Wfin=220nm e L=100nm. Com as simulações iniciais, os transistores com Wfin=220nm apresentaram um valor da tensão de limiar bem próximo dos demais Wfin. Para explorar o porquê de os dispositivos experimentais apresentarem um deslocamento no VT, foi analisada a condução pela segunda interface, onde, com as simulações com cargas fixas na segunda interface, a curva IDSXVGS simulada ficou próxima da experimental, explicando a redução de VT para Wfin=220nm. Com as simulações com cargas fixas na primeira e segunda interfaces, foi possível notar uma imunidade na inclinação de sublimiar ao adicionar essas cargas, que ocorre devido à pequena altura da região ativa de silício (hfin=10nm) que promove um forte acoplamento entre as interfaces. A largura de canal afetou significativamente os valores de DIBL para Ls menores que 100nm, pois, como o campo elétrico é proporcional à área, os transistores com L pequeno e W grande sofrem forte influência desse campo, resultando em um aumento de VT quando em saturação. / Due to the need to obtain integrated circuits (IC) faster and to follow Moore\'s law, it is necessary to reduce the dimensions of the devices increasing the capacity of integration of transistors inside an IC, however, with the miniaturization appears parasitic effects that affect the behavior of the transistors. Therefore, it is necessary to use new devices and the use of different materials to continue the technological evolution. With the advancement of technology, the industries have followed in two different ways, the planar technology (example: UTBB) and the three-dimensional technology (example: FinFET). In this work, these two different geometries are discussed. UTBOX and UTBB (planar) devices and the ?-Gate NW, which has a three-dimensional structure, were analyzed. The use of low-power low-voltage devices has become even more important nowadays, with applications in medical areas such as hearing aids and pacemakers, in smart watches, microsensors, and so on. The lower the power consumed, the lower the heat generated, resulting in a reduction of costs with cooling systems. The circuits that operate in the subthreshold region are used in applications where power consumption is more important than performance, but when working in this region the transistors have a high gain for little voltage variation. In the UTBOX and UTBB SOI nMOSFETs transistors the parameters starting from the threshold voltage towards the region of the transistor in the off state were studied, analyzing the influence of the silicon active region thickness, the channel length and the ground plane implantation in the following parameters: threshold voltage, subthreshold swing, drain-induced barrier lowering (DIBL), gate-induced drain leakage (GIDL) and current ratio on over off (ION/IOFF). The channel length reduction affects all parameters due to the short channel effect, which in addition to reducing the threshold voltage when the device operates with low VDS (VD) and source (VS)), reduces even further when applied high VDS (in saturation), increasing the DIBL. This effect was observed for the nanowire devices with omega gate, in the three channel width analyzed. With high VDS, there is also more current leakage through the back interface for short channel lengths, which reduces the ION/IOFF ratio. The thinner the channel thickness, the better the coupling between the interfaces, resulting in a better SS, making the values close to the theoretical limit of 60mV/dec at room temperature. In the experimental results, it was possible to observe for the UTBOX and UTBB devices a SS reduction of approximately 20mV/dec, with tsi reduction. The thickness of the active region of the silicon also influences the distribution of the electric field, being directly proportional, that is, the thicker the silicon layer, the greater the electric field. The implementation of the ground plane (GP) has as one of its objectives to reduce the depletion charges that are formed below the buried oxide and thus improve the control of the charges in the channel by the voltage applied at the substrate. These depletion charges increase the effective thickness of the buried oxide and also influence the charges at the channel, resulting in a higher potential at the second interface (buried channel/oxide), facilitating the conduction in the channel, i.e., reducing the value of VT. And with the presence of GP, the potential in the second interface is closer to zero, which reduces the conduction by this region, and then, this will require a higher voltage to invert the channel. However, the charge control by the voltage applied at the gate is higher. Values extracted of VT without GP were approximately 0.25V and with GP approximately 0.45V. The study on the omega-gate nanowire transistors of N and P type was based on three parameters: threshold voltage, subthreshold swing and DIBL, with different channel lengths and widths, being possible to observe the presence of the short channel effect for the three analyzed parameters and L=100 and 40nm. The transistors with Wfin=220nm had a higher VT in relation to the others, suggesting the presence of the narrow channel effect, to explore this fact, numerical simulations of N type transistors with Wfin=220nm and L=100nm were done. With the initial simulations, the transistors with Wfin=220nm did not show a narrow channel effect, where the threshold voltage value is very close to the others Wfin. Another alternative that was explored was the conduction by the back interface, where, with the simulations with fixed charges in the back interface, the simulated IDSXVGS curve was close to the experimental one, explaining the reduction of VT for Wfin=220nm. With the simulations with fixed charges in the front and back interfaces it was possible to notice an immunity in the subthreshold swing when adding these charges, which occurs due to the small height of the silicon active region (hfin=10nm) that promotes a strong coupling between the interfaces. The channel width significantly affected the DIBL values for Ls smaller than 100nm since, the electric field is proportional to the area, and the transistors with small L and large W have strong influence of this field, resulting in an increase of VT when in saturation.

Neste trabalho é desenvolvido de forma inédita no Brasil um processo simples de fabricação de transistores FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) com porta de silício policristalino, para servir como base para futuros desenvolvimentos e, também, com finalidade de educação em microeletrônica. É proposta uma sequência de etapas de fabricação necessárias para a obtenção do dispositivo FD SOI nMOSFET, usando apenas 3 etapas de fotogravação e usando o óxido enterrado, intrínseco à tecnologia SOI, como região de campo, objetivando a obtenção do processo mais simples possível e eficiente. São apresentados os procedimentos detalhados de todas as etapas de fabricação executadas. Para obtenção da tensão de limiar de 1V foram fabricadas amostras com 2 doses diferentes de implantação iônica, 1,0x1013cm-2 e 1,2x1013cm-2. Estas doses resultaram em tensões de limiar (VTH) de 0,72V e 1,08V; respectivamente. Como esperado, a mobilidade independente de campo (0) é maior na amostra com dose menor, sendo de 620cm²/Vs e, para a dose maior, 460cm²/Vs. A inclinação de sublimiar é calculada através da obtenção experimental do fator de acoplamento capacitivo () 0,22; para as duas doses, e resulta em 73mV/déc. O ganho intrínseco de tensão (AV) mostrou-se maior na amostra com maior dose em função da menor condutância de saída, sendo 28dB contra 26dB para a dose menor, no transistor com L=40m e W=12m. Desta forma foi possível implementar uma sequência simples de fabricação de transistores SOI, com resultados elétricos relevantes e com apenas 3 etapas de fotogravação, fato importante para viabilizar seu uso em formação de recursos humanos para microeletrônica. / In this work is developed in an unprecedented way in Brazil a simple process of manufacturing transistors FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) with gate polysilicon, to serve as the basis for future developments and also with the purpose of education in microelectronics. A sequence of manufacturing steps necessary for obtaining FD SOI nMOSFET device is proposed, using only three photolithographic steps and using the buried oxide, intrinsic to SOI technology such as field region, aiming to get the simplest possible and efficient process. All the detailed manufacturing steps performed procedures are presented. To obtain the threshold voltage of 1V samples with 2 different doses of ion implantation (1.0x1013cm-2 and 1.2 x1013cm-2) were fabricated. These doses resulted in threshold voltages (VTH) of 0.72 V and 1.08 V, respectively. As expected, mobility independent of field (0) is higher in the sample with the lowest dose, 620cm²/Vs, and for the higher dose, 460cm²/Vs. The subthreshold slope is calculated by obtaining experimental capacitive coupling factor () 0.22, for both doses and results in 73mV/déc. The intrinsic voltage gain (AV) was higher in the sample with a higher dose due to lower output conductance, 28dB against 26dB to the lowest dose, to the transistor with L = W = 40m and 12m. This made it possible to implement a simple sequence of manufacturing SOI transistors with relevant electrical results and with only 3 steps photolithographic important fact to enable their use in training human resources for microelectronics.

L'oxyde de grille des composants peut subir un claquage suite au passage d'un ion lourd unique au travers d'un événement appelé « Single Event Gate Rupture » (SEGR). Dans certains cas, aucune dégradation apparente n'est observée après irradiation bien qu'une interaction ait eue lieu au sein de la couche d'oxyde. Nous parlons alors de la création de défauts latents au sein de la couche isolante. L'objet de cette thèse consiste à évaluer l'impact de ce type de défaut sur la dé-fiabilisation des systèmes de conversion d'énergie embarqués à bord des satellites. En Europe, les principaux maîtres d'œuvre dans la fabrication des satellites se trouvent aujourd'hui face au problème que pose la prise en compte de ces défauts latents. En effet, pour garantir la fiabilité du système de conversion d'énergie, les transistors MOS de puissance doivent suivre une procédure de qualification radiation basée sur la méthode de test militaire américaine MIL-STD-750E/1080. Cette méthode est identique en tout point au standard européen mais recommande en plus, d'effectuer un stress électrique post radiation (Post Gate Stress Test, PGST) afin de révéler la présence d'éventuels défauts latents créés pendant l'irradiation. L'objet de ce travail est d'amener des résultats scientifiques permettant de statuer sur la pertinence du PGST. / At present, space actors are highly concerned with heavy ion-induced power MOSFETs hard failures and in particular by oxide rupture after heavy ion irradiations. In order to guarantee the reliability of space systems, contractors have to follow qualification procedures. The US military standard for heavy ion testing, MIL-STD-750E method 1080, recommends performing a post irradiation test (Post Gate Stress Test PGST) in order to reveal latent defects sites that might have been created during irradiation. Unfortunately, this type of test can only be considered as a pass or fail test. With a too much restrictive approach, rare are the devices to be qualified. Even if the US test method is accurate on most of the points, the main issue is related to the Post-irradiation Gate Stress. What is lacking is that this part of the US Test Standard has neither been dedicated to real space missions nor adapted to space environment. The PGST has even no physical basis justifying performing it for space applications. Working from fundamental to applicative, we aim at drawing test standards dedicated to the engineer in charge of space applications. The qualification of power MOSFETs for space applications is one of the major challenges for European space actors. The goal of this thesis is first to focus on latent defects formation criteria and then, to show under which conditions the post irradiation gate stress test might be relevant or not.

Les magnétomètres à induction sont utilisés dans de nombreux domaines d'exploration scientifique de la géophysique à l'astrophysique. Dans ces deux domaines l'étude des composantes magnétiques des ondes électromagnétiques naturelles requiert des instruments particulièrement performants: sensibles et présentant de faibles bruits intrinsèques pour accéder à des champs magnétiques de quelques fT/ . Dans le cas d'instruments scientifiques embarqués à bord de satellites, des contraintes en température, consommation, encombrement et de tenue en radiation s'ajoutent aux autres contraintes. Les technologies de circuits intégrés permettent une rupture technologique qui se traduit par une réduction de la taille des circuits électroniques embarqués d'un facteur supérieur à 1000 tout en améliorant les performances électriques et instrumentales (réduction de la consommation, des sources de bruit, augmentation de la bande passante et durcissement de l'électronique). Une première thèse au L2E (A. Rhouni) a montré la pertinence d'une technologie CMOS pour ce type d'instrumentation. Dans la présente thèse est décrite l'étude menée sur les circuits intégrés soumis à des environnements contraignants liés aux futures missions dans lesquelles ce type d'instrument doit être embarqué (Mission JUICE de l'ESA). Ces contraintes devenant de plus en plus sévères (dose de radiations supérieure à 300krad, température inférieure à 100 Kelvin ...), leur prise en compte dans tout le processus de conception est nécessaire. Une modélisation des effets de ces contraintes sur les composants de la technologie cible de circuits intégrés a été réalisée afin de pouvoir prendre en compte ces effets dès la conception. Enfin, ces modèles ont servi à la conception d'un circuit de lecture d'un magnétomètre à induction pour l'astrophysique. / Induction magnetometers are used in many fields of scientific exploration from geophysics to astrophysics. In these two fields, the study of the magnetic components of natural electromagnetic waves requires particularly powerful instruments: sensitive and with low intrinsic noises to access magnetic fields of some fT/ . In the case of scientific instruments carried on satellites, constraints on temperature, consumption, congestion and radiation resistance are added to the other constraints. Integrated circuit technologies allow technological breakthrough, which results in a reduction in the size of embedded electronic circuits by a factor greater than 1000, while improving electrical and instrumental performances (reduction in consumption, noise sources, bandwidth and hardening of the electronics). A first thesis at the L2E (A. Rhouni) showed the relevance of a CMOS technology for this type of instrumentation. In this thesis, we describe the study conducted on integrated circuits subject to environmental constraints related to the future missions in which this type of instrument must be embarked (Mission JUICE of ESA). These constraints are becoming more and more severe (radiation dose > 300krad, temperature less than 100 Kelvin ...), taking into account throughout the design process is necessary. A modeling of the effects of these constraints on the components of the integrated circuits technology has been carried out in order to be able to take these effects into account from the design stage. Finally, these models were used to design an induction magnetometer readout circuit for space instrumentation.

Les convertisseurs électroniques de puissance sont voués à fonctionner sous des conditions applicatives de plus en plus sévères tout en respectant les impératifs d’efficacité énergétique et de fiabilité. Or, les besoins industriels tendent vers un plus haut niveau d’intégration fonctionnelle tout en améliorant le rapport qualité-prix. Dès lors, la solution utilisée pour le report des puces semi-conductrices est le siège de densités de courant importantes et d’un flux thermique élevé. La présence de défauts dans cette couche d’interconnexion peut conduire à la dégradation de ses performances et au vieillissement prématuré du composant. L’objectif de nos recherches est d’évaluer la pertinence d’une méthodologie basée sur la confrontation de simulations numériques et de campagnes expérimentales. L’objectif est d’améliorer la compréhension du comportement électrothermique en régime de conduction d’un transistor MOSFET en présence d’un void dans sa brasure. Dans cette manuscrite, nous présenterons la construction d’un modèle intégrant le couplage électrothermique de la partie active qui sera confronté à la réponse de résultats expérimentaux. Puis, une étude numérique basée sur la théorie des plans fractionnaires, qui minimise le nombre de simulations, sera exploitée afin de quantifier l’impact de la taille et de la position du défaut sur la réponse électrothermique du composant et de ses liaisons électriques. Les détails de la mise en place d’une étude expérimentale analogue permettront de mettre en perspective la complémentarité de cette approche. / Power converters nowadays are required to function under harsh conditions in meeting energy efficiency and reliability requirement. Whereas, industrial specifications tend toward a higher level of power integration in respect to the cost constraint. As a result, the die attach is one of the key elements in power module packaging because of high current densities and high heat flow which are transported through. Void formation in the die attach may lead to performance degradation and premature aging of the component. This study introduces a methodology based on the comparison of numerical simulations and experimental campaigns. The obtained results help to improve our understanding on the electro-thermal behaviour of MOSFETs with solder voids. In this thesis, we depict a finite element model in which electro-thermal coupling of a MOSFET active layer is taken in to account. Simulation results will be correlated to the experimental responses. Later on, a parametric numerical study based on the response surface method (RSM) which minimizes the number of simulations and future tests will be exploited to quantify the impact of void position and size on several selective performance criteria. A future serial experimental study in respect to the same RSM design is expected in prospect, in order to fulfil the complementarity for this approach.

Mes travaux de thèse dans les laboratoires SATIE de ENS de Cachan et Ampère de l’INSA de Lyon se sont déroulés dans le cadre du projet Gestion OptiMisée de l'Energie (GENOME) pour étudier le potentiel de certains composants de puissance (JFET, MOSFET et BJT) en carbure de silicium (SiC) dans des convertisseurs électroniques de puissance dédiés à des applications aéronautiques suite au développement de l'avion plus électrique. La première partie de mes travaux étudie la robustesse de MOSFET et BJT en SiC soumis à des régimes de court circuit. Pour les MSOFET SiC, en soumettant ces transistors à la répétition de plusieurs courts-circuits, nous observons une évolution du courant de fuite de grille qui semble être un bon indicateur de vieillissement. Nous définissons une énergie critique répétitive pour évaluer la robustesse à la répétition de plusieurs courts-circuits. Aucun effet significatif de la température ambiante n’a pu être mis en évidence sur la robustesse des MOSFET et BJT SiC sous contraintes de court-circuit. Pour les MOSFET, nous avons également constaté une élévation significative du courant de fuite de grille en augmentant de 600V à 750V la tension, ce qui se traduit également par une défaillance plus rapide. Après ouverture des boîtiers des MOSFET Rohm ayant présenté un court-circuit entre grille et source après défaillance, on remarque une fusion de la métallisation de source qui vient effectivement court-circuiter grille et source. Dans ce mode de défaillance particulier, le court-circuit entre grille et source auto-protège la puce en lui permettant de s’ouvrir.La deuxième partie de ce mémoire est consacrée à l’étude de JFET, MSOFET et BJT SiC en régime d’avalanche. Les JFET de SemiSouth et les BJT de Fairchild présentent une bonne robustesse à l’avalanche. Mais le test d'avalanche révèle la fragilité du MOSFET Rohm puisqu’il entre en défaillance avant d’entrer en régime d’avalanche. La défaillance du MOSFET Rohm et sa faible robustesse en régime d’avalanche sont liées à l’activation du transistor bipolaire parasite. Le courant d'avalanche n’est qu’une très faible partie du courant dans l’inductance et circule du drain/collecteur à la grille/base pour maintenir le transistor en régime linéaire. Une résistance de grille de forte valeur diminue efficacement le courant d'avalanche à travers la jonction drain-grille pour le JFET.La troisième partie concerne l’étude de la commutation de BJT SiC à très haute fréquence de découpage. Nous avons dans un premier temps cherché à valider des mesures de pertes par commutation. Après avoir vérifié l'exactitude de la méthode électrique par rapport à une méthode calorimétrique simplifiée, nous montrons que la méthode électrique est adaptée à l’estimation des pertes de commutation mais nécessite beaucoup d’attention. En raison de mobilité élevée des porteurs de charge dans le SiC, nous montrons que le BJT SiC ne nécessite pas l’utilisation de diode d’anti-saturation. Enfin, aucune variation significative des pertes de commutation n’a pu être constatée sur une plage de température ambiante variant de 25°C à 200°C.La quatrième partie concentre l’étude du comportement de MOSFET SiC sous contraintes HTRB (High Temperature Reverse Bias) et dans une application diode-less dans laquelle les transistors conduisent un courant inverse à travers le canal, exception faite de la phase de temps mort pendant laquelle c’est la diode de structure qui assurera la continuité du courant dans la charge. Les résultats montrent que la diode interne ne présente aucune dégradation significative lors de la conduction inverse des MOSFET. Le MOSFET Cree testé montre une dérive de la tension de seuil et une dégradation de l’oxyde de grille qui sont plus significatives lors des essais dans l’application diode-less que sous des tests HTRB. La dérive de la tension de seuil est probablement due au champ électrique intense régnant dans l’oxyde et aux pièges de charge dans l'oxyde de grille. / My PhD work in laboratories SATIE of ENS de Cachan and Ampère of INSA de Lyon is a part of project GEstioN OptiMisée de l’Energie (GENOME) to investigate the potential of some Silicon carbide (SiC) power devices (JFET, MOSFET and BJT) in power electronic converters dedicated to aeronautical applications for the development of more electric aircraft.The first part of my work investigates the robustness of MOSFET and SiC BJT subjected to short circuit. For SiC MOSFETs, under repetition of short-term short circuit, a gate leakage current seems to be an indicator of aging. We define repetitive critical energy to evaluate the robustness for repetition of short circuit. The effect of room temperature on the robustness of SiC MOSFET and BJT under short circuit stress is not evident. The capability of short circuit is not improved by reducing gate leakage current for MOSFET, while BJT shows a better robustness by limiting base current. For MSOFET, a significant increase in gate leakage current accelerates failure for DC voltage from 600V to 750V. After opening Rohm MOSFETs with a short circuit between gate and source after failure, the fusion of metallization is considered as the raison of failure. In this particular mode of failure, the short circuit between gate and source self-protects the chip and opens drain short current.The second part of the thesis is devoted to the study of SiC JFET, MSOFET and BJT in avalanche mode. The SemiSouth JFET and Fairchild BJT exhibit excellent robustness in the avalanche. On the contrary, the avalanche test reveals the fragility of Rohm MOSFET since it failed before entering avalanche mode. The failure of Rohm MOSFET and its low robustness in avalanche mode are related to the activation of parasitic bipolar transistor. The avalanche current is a very small part of the current in the inductor. It flows from the drain/collector to the gate/base to drive the transistor in linear mode. A high-value gate resistance effectively reduces the avalanche current through the drain-gate junction to the JFET.The third part of this thesis concerns the study of switching performance of SiC BJT at high switching frequency. We initially attempted to validate the switching loss measurements. After checking the accuracy of the electrical measurement compared to calorimetric measurement, electrical measurement is adopted for switching power losses but requires a lot of attention. Thanks to high carrier charge mobility of SiC material, SiC BJT does not require the use of anti-saturation diode. Finally, no significant variation in switching losses is observed over an ambient temperature range from 25°C to 200°C.The fourth part focuses on the study of SiC MOSFET behavior under HTB (High Temperature Reverse Bias) and in diode-less application in which the transistors conduct a reverse current through the channel, except for the dead time during which the body diode ensure the continuity of the current in the load. The results show that the body diode has no significant degradation when the reverse conduction of the MOSFET. Cree MOSFET under test shows a drift of the threshold voltage and a degradation of the gate oxide which are more significant during the tests in the diode-less application than under HTRB test. The drift of the threshold voltage is probably due to intense electric field in the oxide and the charge traps in the gate oxide.

Le fort développement actuel des systèmes électroniques embarqués nous conduit à relever le défi de leur fiabilisation, ceci d’autant plus que des organes de sécurité sont souvent concernés et que ces systèmes opèrent dans des conditions environnementales difficiles avec une exigence de réduction de coût drastique. Ce qui caractérise le mieux l’évolution récente de ces systèmes électroniques embarqués c’est une forte intégration qui conduit à réduire leur encombrement et leur poids tout en augmentant la puissance électrique convertie. Il en résulte automatiquement une augmentation de la densité de puissance dissipée et l’étude de leur comportement électrothermique prend, dans ces conditions, une importance fondamentale. Le présent travail concerne le développement d’outils précis de modélisation électrothermique qui permettent d’appréhender l’impact de la technologie choisie (conception, connectiques, matériaux …) sur les phénomènes causés par les défauts qui apparaissent avec le vieillissement. Des règles de robustesse spécifiques à chaque technologie pourront être édictées à l’aide de simulations 3D distribuées présentées dans le mémoire. Dans un premier temps la modélisation électrothermique compacte a été abordée. Ensuite, en se limitant aux modules MOS de puissance, une première classe de problèmes caractérisée par l’absence de commutation peut être traitée en ayant recours à une modélisation électrothermique par éléments finis qui considère que le composant est constitué par un ensemble de zones de résistivités électriques et de conductivités thermiques différentes. Une tentative a été faite en vue d’étendre l’étude électrothermique aux classes de problèmes mettant en œuvre des MOS de puissance fonctionnant en régime de commutation. Le modèle électrique distribué doit alors être capable de calculer et de répartir les pertes totales (état passant, état bloqué et commutation) pour un régime de commutation rapide. Enfin, un soin particulier a été accordé à l’étude du fonctionnement en avalanche, une méthode basée sur l’expérimentation et l’utilisation d’un modèle électrothermique simple afin d’estimer la température de jonction d’un MOSFET de puissance lors de son fonctionnement en régime d’avalanche de courte durée a été développée. Pour conclure, on a démontré qu’il n’existe pas une réponse unique en termes de modélisation électrothermique et que chaque méthode vise à résoudre une classe spécifique de problèmes / The strong current development of embedded electronic systems leads us to the challenge of their reliability, all the more so as the security organs are often involved and that these systems operate in harsh environmental conditions with a requirement to reduce cost drastically. What best characterizes the recent evolution of the embedded electronic systems is a strong integration that leads to reduce their size and weight while increasing the electrical power converted. This automatically increases the power density dissipated and so the study of their electro-thermal behavior becomes of fundamental importance. The present work concerns the development of specific tools that allow electro-thermal modeling to understand the impact of the chosen technology (design, connections, materials ...) on the phenomena caused by defects that occur with ageing. Robustness rules specific to each technology may be adopted using 3D simulations presented in the report. At first, compact electro-thermal modeling was discussed. Second, considering power MOS modules which operate in a non-switching mode, a first class of problems can be treated by using a finite element electro-thermal modeling that assumes that the components act as a set of zones whose electrical and thermal conductivities are different. An attempt was made to extend the electro-thermal study to classes of problems where power MOSFETs are switching. Distributed electrical models must then be able to calculate and allocate total losses (on-state, off-state and switching) for a fast switching rate. Finally, particular attention has been given to the study of avalanche mode operation; a method based on experimentation and the use of a simple electro-thermal model to estimate the junction temperature of a power MOSFET when operating in short duration avalanche mode has been developed. To conclude, we have demonstrated that there is no single answer in terms of electro-thermal modeling and each method developed aims to solve a specific class of problems

No description available.

For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.