The motivation to study this non-classical CMOS device is necessary to face with the ITRS constraints. In the ITRS roadmap, the gate length of devices are being scaled down rapidly but this rapid scaling is not in pace with the relatively slow scaling of the gate equivalent oxide thickness which leads to a degradation in the performance of the transistor. One of the solutions to this problem is the use of non-classical devices, such as the Gate-All-Around (GAA) MOSFET. Owing to the flexibility of SOI technology, these novel devices can be adapted to this technology bringing along with it the benefit of SOI technology. One of the main advantage of building this GAA device on SOI technology is that it offers the possibility whereby the second gate is easily built into the back of the device. GAA devices are also interesting because they do not need to scale down the thickness of the gate oxide rapidly but still able to maintain a suitable thickness to avoid problems such as current leakage through the thin gate oxide by tunnelling. The objective of this research can be divided into three parts; the first is to study the feasibility of the various fabrication process for this GAA device, the second to analyse the electrical characteristics of these fabricated GAA devices from DC characteristics up to 110 GHz and the third one is the use of commercial numerical simulation softwares (IE3D, Silvaco) in order to describe the physics of these novel devices. In this study, these different structures shows advantages and disadvantages when used in either analog or RF applications. The graded-channel structure has shown that it is advantageous when used in high performance analog circuits. The advantages of this structure is further enhanced when it is combined with the double-gate structure, forming a double-gate graded channel SOI MOSFET. Optimizing in terms of doping level along the channel of the graded-channel is important to yield good electrical results. In order for these devices to be successful commercially, it is important that they are compatible with the fabrication technology and trends available today and in the near future. To confirm that these devices can be adapted into today's and tomorrow's technology, we have shown that these they are easily adaptable in the current technology. Multiple-gate devices are a new group of devices which have been identified by ITRS as potential devices to meet the demands in the future. In this study, we have shown that these multiple-gate devices do indeed show improved short-channel effects and improved analog and RF characteristics when compared to the single-gate devices in existence. One of the main contributors to these improvements is due to what is known as the “volume inversion”.

Many trends in the silicon industry could be interpreted as the herald of the end of traditional Si scaling. If this premise holds, future performance and system-on-chip applications may not be reached with conventional Si technology extensions. We review progress towards our vision that a larger crystal structure on Si, namely relaxed SiGe epitaxial layers, can support many generations of higher performance Si CMOS and new system-on-chip functionality without the expense of significant new equipment and change to CMOS manufacturing ideology. We will review the impact of tensile strained Si layers grown on relaxed SiGe layers. Both NMOS and PMOS exhibit higher carrier mobilities due to the strained Si MOSFET channel. Heterostructure MOSFETs designed on relaxed SiGe can have multiple-generation performance increases, and therefore determine a new performance roadmap for Si CMOS technology, independent of MOSFET gate length. We also indicate that this materials platform naturally leads to incorporating new optical functionality into Si CMOS technology. / Singapore-MIT Alliance (SMA)

We have fabricated strained Ge channel p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si₀.₃Ge₀.₇ virtual substrates. The poor interface between silicon dioxide (SiO₂) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400° C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly 8 times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm²/V-s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement mode MOSFET with buried channel-like transport characteristics. / Singapore-MIT Alliance (SMA)

The importance of simulation is increasing in the researchon semiconductor devices and materials. Simulations are used toexplore the characteristics of novel devices as well asproperties of the semiconductor materials that are underinvestigation, i.e. generally materials where the knowledge isinsufficient. A wide range of simulation methods exists, andthe method used in each case is selected according to therequirements of the work performed. For simulations of newsemiconductor materials, extremely small devices, or deviceswhere non-equilibrium transport is important, the Monte Carlo(MC) method is advantageous, since it can directly exploit themodels of the important physical processes in the device. One of the semiconductors that have attracted a lot ofattraction during the last decade is silicon carbide (SiC),which exists in a large number of polytypes, among which3C-SiC, 4H-SiC and 6H-SiC are most important. Although SiC hasbeen known for a very long time, it may be considered as a newmaterial due to the relatively small knowledge of the materialproperties. This dissertation is based on a number of MCstudies of both the intrinsic properties of different SiCpolytypes and the qualities of devices fabricated by thesepolytypes. In order to perform these studies a new full-bandensemble device MC simulator, the General Monte CarloSemiconductor (GEMS) simulator was developed. Algorithmsimplemented in the GEMS simulator, necessary when allmaterial-dependent data are numerical, and for the efficientsimulation of a large number of charge carriers in high-dopedareas, are also presented. In addition to the purely MC-relatedstudies, a comparison is made between the MC, drift-diffusion,and energy-balance methods for simulation of verticalMESFETs. The bulk transport properties of electrons in 2H-, 3C-, 4H-and 6H-SiC are studied. For high electric fields the driftvelocity, and carrier mean energy are presented as functions ofthe field. For 4H-SiC impact-ionization coefficients,calculated with a detailed quantum-mechanical model ofband-to-band tunneling, are presented. Additionally, a study oflow-field mobility in 4H-SiC is presented, where the importanceof considering the neutral impurity scattering, also at roomtemperature, is pointed out. The properties of 4H- and 6H-SiC when used in short-channelMOSFETs, assuming a high quality semiconductor-insulatorinterface, are investigated using a simple model for scatteringin the semiconductor-insulator interface. Furthermore, theeffect is studied on the low and high-field surface mobility,of the steps formed by the common off-axis-normal cutting ofthe 4H- and 6H-SiC crystals. In this study an extension of theprevious-mentioned simple model is used.

This report is the basis for a Bachelor of Science thesis in engineering done at Volvo Powertrain in Gothenburg. The problem consisted of investigating a circuit with a PWM-controlled MOSFET driving a DC-motor. The problem was to investigate what caused the circuit to break the transistor. Finally an improvement of the circuit is designed making the MOSFET withstand the stressful conditions exposed to. An overall description of the problems with switching an inductive load using a MOSFET as switch is done. Some methods to protect the MOSFET from failure are also discussed. Finally a discussion is held to suggest what broke the MOSFET, and an improved design is proposed.

In modern times the increasing complexity of transistors and their constant decreasingsize require more effective techniques to display and interpret the processes that are inside of devices. In this work, we are modeling a two‐dimensional n‐MOSFET with a long channeland uniformly doped substrate. We assume that this device is a large geometry device so that short‐channel and narrow‐width effects can be neglected. As a result of the thesis, a demonstration program was built. In this executable file, the user can choose parameters of the MOSFET‐model: drain and gate voltage, and different geometrical parameters of the device (junction depth and effective channel length). In the advanced regime of the program, the user can also specify the model re‐calculation parameter, doping concentration in n+ and bulk regions. The program shows the channel between the source and drain region with surface diagrams of carrier density and potential energy as an output. It is possible to save all calculated results to a file and process it in any other program, for example, plot graphics in Matlab or Matematica. The model can be used in lectures that are related to semiconductor physics in order to explain the basic working mechanisms of MOSFETs as well as for further detailed analysis of the processes in MOSFETs. It is possible to use our modeling techniques to rebuild the model in another computer language, or even to build other models of transistors, performing similar calculations and approximations. It is possible to download the executable file of the model here: http://studentdevelop.com/projects/MOSFET_model.zip

The objective of this research is to comprehensively compare bulk accumulation and inversion MOSFETs, and find application areas where each is superior.Short channel effect (SCE) models for accumulation and inversion MOSFETs are derived that accurately predict threshold voltage, subthreshold swing, and subthreshold current. A source/drain junction depth dependent characteristic length is derived that can be used to rapidly assess the impact of junction depth scaling on minimum channel length. A fast circuit simulation methodology is developed that uses physically based I-V models to simulate inversion and accumulation MOSFET inverter chains, and is found to be accurate over a wide range of supply voltages. The simulation methodology can be used for rapid technology optimization, and performance prediction. Design guidelines are proposed for accumulation MOSFET design; the guidelines result in a low process sensitivity, low SCE, and a subthreshold current less than the allowable limit. The relative performance advantage of accumulation/inversion MOSFETs is gate-technology dependent. In critical comparisons, on-current is evaluated by means of a full band Monte Carlo device simulation. Gate-leakage, and band-to-band tunneling leakage at the drain-substrate region are included in the performance analysis. For mid-bandgap metal gate, accumulation MOSFETs perform better than inversion MOSFETs for hi-performance (HiP) and low-operating power (LOP) applications. For tunable metal gate technology, inversion MOSFETs always perform better than accumulation MOSFETs. For dual poly technology, accumulation MOSFETs perform better than inversion MOSFETs for low standby power (LSTP) applications. A comprehensive scaling analysis has been performed on accumulation and inversion MOSFETs using both SCE models and 2-D simulations. Results show that accumulation MOSFETs can scale better than inversion MOSFETs for mid-bandgap metal gate HiP, and LOP applications; and poly gate LSTP applications.

This thesis describes advanced modeling of nanoscale bulk MOSFETs incorporating critical quantum mechanical effects such as gate direct tunneling and energy quantization of carriers. An explicit expression of gate direct tunneling for thin gate oxides has been developed by solving the Schroinger equation analytically. In addition, the impact of different gate electrode as well as gate insulation materials on the gate direct tunneling is explored. This results in an analytical estimation of the potential solutions to excessive gate leakage current. The energy quantization analysis involves the derivation of a quantum mechanical charge distribution model by solving the coupled Poisson and Schroinger equations. Based on the newly developed charge distribution model, threshold voltage and subthreshold swing models are obtained. A transregional drain current model which takes into account the quantum mechanical correction on device parameters is derived. Results from this model show good agreement with numeric simulation results of both long-channel and short-channel MOSFETs.The models derived here are used to project MOSFET scaling limits. Tunneling and quantization effects cause large power dissipation, low drive current, and strong sensitivities to process variation, which greatly limit CMOS scaling. Developing new materials and structures is imminent to extend the scaling process.

This work investigates the influence of gate-induced floating body effect (GIFBE) on negative bias temperature instability (NBTI) in partial depleted silicon-on-insulator p-type metal-oxide-semiconductor field effect transistors (PD-SOI p-MOSFETs). The results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be attributed to the electrons tunneling from the process-induced partial n+ poly gate, and at higher voltages is dominated by the proposed anode electron injection (AEI) model. Moreover, when introducing the mechanical strain to PD-SOI p-MOSFETs result in decreasing the NBTI degradation for BC and FB devices, because increase of effective mass of hole and barrier height to decrease the probability of reaction of NBTI. The degradation of NBTI on FB device less than BC device because of strain-induced band gap narrowing to substrate and p+ poly gate, resulting in the rising of rate of impact ionization in AEI model to increase the accumulation of electrons on body. After that, giving the drain voltage in NBTI stress, the threshold voltage, Vth, shift decreases as drain voltage (VD) rising within the stress condition of VD= -1V. This phenomenon can be attributed to the shorter effective reaction time of hole and Si-H bonds after applying drain voltage during NBTI stress. However, beyond the condition at VD= -1V, the Vth shift rises as the drain voltage increasing. This behavior is resulted from the self-heating effect induced by the higher stress VD to increase the degradation of NBTI.

In this paper, several new MOSFET devices, vertical MOSFET with L-shaped internal block layers (bVMOS), planar MOSFET with self-aligned internal block layers (bMOS), and Silicon-Germanium MOSFET with self-aligned internal block layers (bSGMOS) are presented. We use the sidewall spacer and etch back techniques to form the L-shaped internal block layers of bVMOS. They can suppress the short channel effects, diminish the parasitic capacitance, and reduce the leakage current cause by P-N junction between source/drain and body regions. They also provide a pass way to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, we use Si3N4 cap layer upon gate as a hard mask, combining self-aligned and sidewall spacer techniques to fabricate the internal block layers under the both sides of channel end to form bMOS. The depleted region between source/drain and body is shielded and so the short channel effects and the controllability of gate to channel are improved. The internal block layers not only maintain the character of internal block layers but also ameliorate the drawback of bVMOS. The ISE TCAD simulation results show the short channel effect is suppressed and the thermal instability is improved by the internal block layers effectively in each device. Furthermore, we employ the epitaxial silicon-germanium thin film process (bSGMOS) to form silicon-germanium thin film at source/drain region to improve the device current drive by the strain thereby enhancing the device performance.