Die vorliegende Arbeit beschreibt die Berechnung und Optimierung von Silicon-On-Insulator-Metal-Oxide-Semiconductor-Field-Effect-Transistors, einschließlich noch nicht in Massenproduktion hergestellter neuartiger Transistorarchitekturen für die nächsten Technologiegenerationen der hochleistungsfähigen Logik-MOSFETs mit Hilfe der Prozess- und Bauelementesimulation. Die neuartigen Transistorarchitekturen umfassen dabei vollständig verarmte SOI-MOSFETs, Doppel-Gate-Transistoren und FinFETs. Die statische und dynamische Leistungsfähigkeit der neuartigen Transistoren wird durch Simulation bestimmt und miteinander verglichen. Der mit weiterer Skalierung steigende Einfluss von statistischen Variationen wird anhand der Oberflächenrauheit sowie der Polykantenrauheit untersucht. Zu diesem Zweck wurden Modelle für die Generierung der Rauheit erarbeitet und in das Programmsystem SIMBA implementiert. Die mikroskopische Rauheit wird mit der makroskopischen Bauelementesimulation kombiniert und deren Auswirkungen auf die Standardtransistoren und skalierte Bauelemente aufgezeigt. Zudem erfolgt eine ausführliche Diskussion der Modellierung mechanischer Verspannung und deren Anwendung zur Steigerung der Leistungsfähigkeit von MOSFETs. Die in SIMBA implementierten Modelle zur verspannungs-abhängigen Änderung der Ladungsträgerbeweglichkeit und Lage der Bandkanten werden ausführlich dargestellt und deren Einfluss auf die elektrischen Parameter von MOSFETs untersucht. Weiterhin wird die Verspannungsverteilung für verschiedene Herstellungsvarianten mittels der Prozess-simulation berechnet und die Wirkung auf die elektrischen Parameter dargestellt. Exponential- und Gaußverteilungsfunktionen bilden die Grundlage, um die mechanische Verspannung in der Bauelementesimulation nachzubilden, ohne die Verspannungsprofile aus der Prozesssimulation zu übernehmen. Darüber hinaus werden die Grenzfrequenzen der Logiktransistoren in Bezug auf die parasitären Kapazitäten und Widerstände und zur erweiterten MOSFET-Charakterisierung dargestellt.

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The increasing market demand for wideband gap (WBG) power switches has led to heightened competition to increase converter power density, switching frequencies, and reduce form factor, among other factors. However, this technology has also brought about an increase in encounters with electromagnetic interference (EMI), posing significant challenges. Nevertheless, the maturation of power switches has been accompanied by an improvement in gate drive technology aimed at resolving EMI challenges, albeit at a higher component and cost expense. This thesis aims to design, analyze, and implement a recent innovative differential gate driver for a 1.2 kV SiC MOSFET full bridge module. The purpose of this design is to mitigate EMI, improve performance, and reduce the number of filtering elements that are typically required. The investigation into the impact of EMI on electrical systems involves exploring factors such as testing equipment, power supplies, and gate drive layout. Based on these considerations, system and sub-system level analyses are conducted to derive practical design recommendations for implementing the differential gate driver. Three gate drive PCBs are designed and evaluated through extensive double pulse tests (DPTs). Furthermore, continuous switching of the driver presents its own set of challenges that are not apparent during the DPTs, requiring further exploration of low-cost solutions. Finally, a comparison between custom and discrete module solutions employing 1.2 kV SiC MOSFETs is conducted, highlighting the advantages and disadvantages of each approach. The solutions proposed in this work are intended to be extended to other gate drive ICs, with the goal of providing valuable insights and guidelines for EMI suppression and gate driver performance enhancement. / Master of Science / The increasing demand for powerful and efficient electronic devices has led to competition to develop better converters with wideband gap (WBG) power switches. These switches can make electronics work faster and take up less space, but they can also cause electromagnetic interference (EMI) that can be problematic. Despite these challenges, advances in power switch technology have led to improvements in gate drive technology, which can help reduce EMI, albeit, sometimes, at a higher cost. This research aims to design and analyze an innovative differential gate driver for a 1.2 kV SiC MOSFET full bridge module that can help mitigate EMI, improve performance, and reduce the number of required filtering elements. A system-level analysis is conducted to identify critical noise paths and potential solutions in response to poor gate driver performance. Practical design recommendations are provided for implementing a differential gate driver, and three PCB designs are tested and evaluated to showcase the effectiveness of the proposed solutions. The work also includes a comparison between a custom module and discrete module solutions employing 1.2 kV SiC MOSFETs, highlighting the advantages and disadvantages of each approach. The findings are extended to other gate drivers that share similar performance specifications, demonstrating the potential and improvements that can be achieved with the suggested techniques. Overall, the study provides valuable insights and guidelines for EMI suppression and performance enhancement in power electronics systems utilizing differential gate drivers.

TCAD numerical simulations have been carried out to study the current-voltage, electrical breakdown, and self-heating characteristics of β-Ga2O3 based metal-oxide field effect transistors (MOSFETs). β-Ga2O3 semiconductor has an ultra-wide bandgap of ~ 4.8 eV, a theoretical critical breakdown field strength, Ec ~ 8 MV/cm, making it an excellent candidate for high-voltage or power electronics applications. The numerical simulations have been benchmarked against experimentally reported data. For modeling impact ionization, which is expected to induce intrinsic avalanche breakdown, the Selberherr’s model has been used with appropriate parameterization. For a device with a gate length of 2 μm, 0.6 μm gate-drain spacing, 3.4 μm source-drain spacing, and 20 nm thick Al2O3 gate insulator, the intrinsic breakdown voltage was found to be ~460 V. While self-heating dramatically affects the output current and conductance, it has an insignificant effect on the breakdown voltage. The use of a thinner epitaxial channel was found to increase the breakdown voltage slightly (by ~30 V).

A new multiple-gate transistor, the SOI MOS-JFET, is presented. This device combines the MOS field effect and junction field effect within one transistor body. Measured I-V characteristics are provided to illustrate typical modes of operation and the functionality associated with each gate. Two-dimensional simulations of the device?s cross-section will be presented to illustrate various conduction modes under different bias conditions. Test results indicate the MOS-JFET is well suited for both high-voltage and low-voltage circuit demands for systems-on-a-chip applications on SOI technology. Analog building-block circuits based the MOS-JFET are also presented.

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Medium Voltage (MV) power conversion systems are essential in high power applications to address the increasing demand of energy and the increasing penetration of renewable energy sources. MV power electronics converters are the key elements for power conversion in MV systems and are the focus of this study. Multilevel converter topologies are promising topologies in MV applications because of their reduced voltage stress on devices, excellent output quality, reduced semiconductor losses, lower common mode voltage among other advantages. However, they may suffer from the large number of switching devices and capacitors, as well as the need to regulate capacitor voltages. SiC MOSFETs can achieve higher switching speeds, higher switching frequencies, higher voltage ratings, higher operation temperatures compared to traditional Si devices. They have shown promise to increase the efficiency and power density of the converters, but may suffer from higher voltage overshoots, increased Electromagnetic Interference (EMI) emission and so on. In SiC-based multilevel converters, the features of multilevel topologies, and the features of SiC MOSFETs are coupled together. The benefits, challenges, and solutions of using SiC MOSFETs in multilevel converters are studied explicitly in this work. With the high switching speeds and high switching frequencies of SiC MOSFETs, and the large number of switches and capacitors in multilevel topologies, SiC-based multilevel converters need to be studied while considering high-frequency voltage and current behaviors and the interactions among them at different locations. Firstly, the use of SiC-based multilevel converter in the high-speed motor drive application is explored. A three-phase inverter is designed and built employing five-level Stacked Multicell Converter topology and SiC MOSFETs. The benefits and challenges of using multilevel converter topology and using SiC MOSFETs for this application are explored. A fitting topology is selected, and a prototype is designed, both with attentions paid to deal with the high switching speeds of SiC MOSFETs. The inverter is verified through experiments to meet all specifications with a high efficiency. Then a unique type of converter, converters with Integrated Capacitor Blocked Transistor (ICBT) cells are studied. Unlike the traditional methods, there are no fast-developing voltage unbalances, or high cell capacitor voltage ripples in ICBT-based converters. The ideal operation principle is analyzed and verified by the simulation results. Then the impacts of non-idealities on the operation are analyzed, and a control method is proposed for this type of converter. The operation and control of ICBT-based converters are verified by experimental results to achieve low cell capacitor voltage ripples and excellent voltage balance in Medium Voltage high power applications. Lastly, the conducted EMI emission in SiC-based multilevel converters are studied. Four SiC-based multilevel converters are studied, with the focus on the power circuit in one converter and the auxiliary circuits in the other three converters. The complexity of noise generation and propagation in multilevel converters is presented. The conducted EMI disturbances are experimentally evaluated, analyzed, and effectively mitigated in all four cases. / Doctor of Philosophy / Medium Voltage (MV) power conversion systems are essential in high power applications to address the increasing demand of energy and the increasing penetration of renewable energy sources. MV power electronics converters are the key elements for power conversion in MV systems and are the focus of this study. Multilevel converter topologies are promising topologies in MV applications because of their reduced voltage stress on devices, excellent output quality, reduced semiconductor losses, lower common mode voltage among other advantages. However, they may suffer from the large number of switching devices and capacitors, as well as the need to regulate capacitor voltages. SiC MOSFETs can achieve higher switching speeds, higher switching frequencies, higher voltage ratings, higher operation temperatures compared to traditional Si devices. They have shown promise to increase the efficiency and power density of the converters, but may suffer from higher voltage overshoots, increased Electromagnetic Interference (EMI) emission and so on. In SiC-based multilevel converters, the features of multilevel topologies, and the features of SiC MOSFETs are coupled together. The benefits, challenges, and solutions of using SiC MOSFETs in multilevel converters are studied explicitly in this work. With the high switching speeds and high switching frequencies of SiC MOSFETs, and the large number of switches and capacitors in multilevel topologies, SiC-based multilevel converters need to be studied while considering high-frequency voltage and current behaviors and the interactions among them at different locations. Firstly, the use of SiC-based multilevel converter in the high-speed motor drive application is explored. A three-phase inverter is designed and built employing five-level Stacked Multicell Converter topology and SiC MOSFETs. The benefits and challenges of using multilevel converter topology and using SiC MOSFETs for this application are explored. A fitting topology is selected, and a prototype is designed, both with attentions paid to deal with the high switching speeds of SiC MOSFETs. The inverter is verified through experiments to meet all specifications with a high efficiency. Then a unique type of converter, converters with Integrated Capacitor Blocked Transistor (ICBT) cells are studied. Unlike the traditional methods, there are no fast-developing voltage unbalances, or high cell capacitor voltage ripples in ICBT-based converters. The ideal operation principle is analyzed and verified by the simulation results. Then the impacts of non-idealities on the operation are analyzed, and a control method is proposed for this type of converter. The operation and control of ICBT-based converters are verified by experimental results to achieve low cell capacitor voltage ripples and excellent voltage balance in Medium Voltage high power applications. Lastly, the conducted EMI emission in SiC-based multilevel converters are studied. Four SiC-based multilevel converters are studied, with the focus on the power circuit in one converter and the auxiliary circuits in the other three converters. The complexity of noise generation and propagation in multilevel converters is presented. The conducted EMI disturbances are experimentally evaluated, analyzed, and effectively mitigated in all four cases.

With the development of fuel cell based power systems, the need for more advanced DC-DC power converters has become apparent. In such applications DC-DC converters provide an important link between low voltage fuel cell sources and inverter buses operating at significantly higher voltages. Advancements in converter efficiency, cost reduction, and size reduction are the most necessary. These challenges are formidable, even when considering the improvements made to conventional DC-DC topologies. However, it can be possible to achieve these criteria through the implementation of more advanced topologies. A recently developed efficient three-phase DC-DC topology offers benefits over standard designs. Passive component sizes and output ripple voltage were reduced as a result of an effective boost in switching frequency. Converter output voltage was reached more easily due to an increased transformer voltage boost ratio in addition to the turns ratio. For cost reduction, the converter was designed and built with discrete components instead of more expensive integrated modules. This thesis presents an overview of the three-phase converter, with a detailed focus on the design, implementation, and performance of the switching stage. The functionality of the three-phase topology is covered along with the selection of converter components. Simulation results are shown for both ideal and real converter models. Considerations for the switching device package with respect to circuit board and heat sinking configurations are discussed in support of the selection of an insulated metal substrate (IMS) circuit board. An effective circuit layout designed to minimize parasitic trace inductances as well as provide favorable component positioning is presented. Experimental converter test results are shown and the causes of undesired effects are identified. Switching stage modifications and their results are discussed along with the benefits of proposed future design enhancements. / Master of Science