Avec la diminution constante des dimensions des dispositifs électroniques, les structures MOS font face à de nombreux effets physiques liés à la miniaturisation. Dans le but de maintenir le rythme d'intégration indiqué par la loi de Moore, des nouvelles technologies, dont la structure résiste plus à ces effets physiques, remplacerons le transistor MOSFET bulk. Les modèles physiques permettant de prédire le comportement des transistors MOS atteignent rapidement leurs limites quand ils sont appliqués à ces structures émergentes. Ce travail de thèse est consacré au développement des modèles numériques et analytiques dédiés à la caractérisation des nouvelles architectures SOI et à substrat massif. Nous nous focalisons sur la modélisation du courant de drain basée sur le potentiel de surface, ainsi qu'à la modélisation du comportement en bruit basse fréquence de ces nouveaux dispositifs. Nous proposons un modèle explicite décrivant les potentiels de surface avant et arrière d'une structure SOI. Nous développons ensuite un modèle de bruit numérique et analytique permettant de caractériser les différents oxydes d'une structure FD SOI. La dernière partie de ce mémoire est consacrée à l'étude d'une nouvelle architecture du transistor MOS sur substrat massif. Une caractérisation de la conduction électrique de ce dispositif et de son comportement en bruit basse fréquence sont présentés / With the continuous reduction of the size of MOS devices, various associated short channel effects become significant and limit this scaling. To restrain this limit, multi-gate MOSFET devices seem to be more interesting, thanks to their better control of the gate on the channel. These new devices seem to be good candidates to replace the classical MOS architecture. The existing physical models used to predict the behaviour of MOSFET bulk devices are limited when they are applied to these emerging structures. This thesis is devoted to the development of numerical and analytical models dedicated to the characterization of new SOI architectures and bulk devices. We focus on the modeling of the drain current based on the surface potential as well was the modeling of the low frequency noise behaviour of these devices. We propose an explicit model describing the front and back surface potential of a FD SOI structure. We then develop numerical and analytical low frequency noise models allowing the characterization of the different oxides of a FD SOI structure. The last part of this thesis is devoted to the study of a new architecture of bulk MOS transistors. A characterization of the electrical conduction of this device and its low frequency noise behavior are presented

Selon l’esprit de la “loi de Moore” utilisant des techniques innovantes telles que l’intégration 3D et de nouvelles architectures d’appareils, le marché a également évolué pour commencer à imposer des exigences spécifiques aux composants, comme des appareils à faible consommation et à faible fuite, requis par l’Internet des objets (IoT) applications et périphériques hautes performances demandés par les applications 5-G et les centres de données. Ainsi, le secteur des semi-conducteurs s’est peu à peu laissé guider par les avancées technologiques, mais aussi par les applications.La réduction de la tension d’alimentation est encore plus importante pour les applications à faible puissance, comme dans l’IoT, cela est limité par la variabilité du périphérique. L’abaissement de la tension d’alimentation implique une marge réduite pour que les concepteurs gèrent la variabilité du dispositif. Cela nécessite un accès à des outils améliorés permettant aux concepteurs de prévoir la variabilité des périphériques et d’évaluer son effet sur les performances des leur conception, ainsi que des innovations technologiques permettant de réduire la variabilité des périphériques.Cette thèse se concentre dans la première partie et examine comment la variabilité du dispositif peut être modélisée avec précision et comment sa prévision peut être incluse dans les modèles compacts utilisés par les concepteurs dans leurs simulations SPICE. La thèse analyse d’abord la variabilité du dispositif dans les transistors FD-SOI avancés à l’aide de mesures directes. À l’échelle spatiale, en fonction de la distance entre les deux dispositifs considérés, la variabilité peut être classée en unités de fabrication intra-matrice, inter-matrice, inter-tranche, inter-lot ou même entre différentes usines de fabrication. Par souci de simplicité, toute la variabilité d’une même matrice peut être regroupée en tant que variabilité locale, tandis que d’autres en tant que variabilité globale. Enfin, entre deux dispositifs arbitraires, il y aura des contributions de la variabilité locale et globale, auquel cas il est plus facile de l’appeler la variabilité totale. Des stratégies de mesure dédiées sont développées à l’aide de structures de test spécialisées pour évaluer directement la variabilité à différentes échelles spatiales à l’aide de caractérisations C-V et I-V. L’effet de la variabilité est d’abord analysé sur des facteurs de qualité (FOM) sélectionnés et des paramètres de procédés extraits des courbes C-V et I-V, pour lesquels des méthodologies d’extraction de paramètres sont développées ou des méthodes existantes améliorées. Cette analyse aide à identifier la distribution des paramétres et les corrélations possibles présentes entre les paramètres.Ensuite, nous analysons la variabilité dépendante de la polarisation dans les courbes I-V et C-V. Pour cela, une métrique universelle, qui fonctionne quelle que soit l’échelle spatiale de la variabilité, est definée sur la base de l’analyse des appariement précédemment rapportée pour la variabilité locale. Cette thèse étend également cette approche à la variabilité globale et totale. L’analyse de l’ensemble des courbes permet de ne pas manquer certaines informations critiques dans une plage de polarisation particulière, qui n’apparaissaient pas dans les FOM sélectionnés.Une approche de modélisation satistique est utilisée pour modéliser la variabilité observée et identifier les sources de variations, en termes de sensibilité à chaque source de variabilité, en utilisant un modèle physique compact comme Leti-UTSOI. Le modèle compact est d’abord étalonné sur les courbes C-V et I-V dans différentes conditions de polarisation et géométries. L’analyse des FOM et de leurs corrélations a permis d’identifier les dépendances manquantes dans le modèle compact. Celles-ci ont également été incluses en apportant de petites modifications au modèle compact. / The ``Moore's Law'' has defined the advancement of the semi-conductor industry for almost half a century. The device dimensions have reduced with each new technology node, and the design community and the market for the semiconductor have always followed this advancement of the industry and created applications which took better advantage of these new devices. But during the past decade, with the device dimensions approaching the fundamental limits imposed by the materials, the pace of this scaling down of device dimensions has decreased. While the technology struggled to keep alive the spirit of ``Moore's Law'' using innovative techniques like 3-D integration and new device architectures, the market also evolved to start making specific demands on the devices, like low power, low leakage devices demanded by Internet of Things (IoT) applications and high performance devices demanded by 5-G and data centre applications. So the semiconductor industry has slowly moved away from being driven by technology advancement, and rather it is now being driven by applications.Increasing power dissipation is an unavoidable outcome of the scaling process, while also targeting higher frequency applications. Historically, this issue has been handled by replacing the basic transistors (BJTs by MOSFETs), freezing the operation frequency in the system, lowering supply voltage, etc. The reduction of supply voltage is even more important for low power applications like in IoT, but this is limited by the device variability. Lowering the supply voltage implies reduced margin for the designers to handle the device variability. This calls for access to improved tools for the designers to predict the variability in the devices and evaluate its effect on the performance of their design and innovations in technology to reduce the variability in the devices. This thesis concentrates in the first part, and evaluates how the device variability can be accurately modelled and how its prediction can be included in the compact models used by the designers in their SPICE simulations.At first the thesis analyses the device variability in advanced FD-SOI transistors using direct measurements. In the spatial scale, depending on the distance between the two devices being considered, the variability can be classified into intra-die, inter-die, inter-wafer, inter-lot or even between different fabs. For the sake of simplicity all the variability within a single die can be grouped together as local variability, while others as global variability. Finally between two arbitrary device, there will be contributions from both local and global variability, in which case it is easier to term it as the total variability. Dedicated measurement strategies are developed using specialized test structures to directly evaluate the variability in different spatial scales using C-V and I-V characterisations. The effect of variability is first analysed on selected figure of merits (FOMs) and process parameters extracted from the C-V and I-V curves, for which parameter extraction methodologies are developed or existing methods are improved. This analysis helps identify the distribution of the parameters and the possible correlations present between the parameters.A very detailed analysis of the device variability in advanced FD-SOI transistors is undertaken in this thesis and a novel and unique characterisation and modelling methodology for the different types of variability is presented in great detail. The dominant sources of variability in the device behaviour, in terms of C-V and I-V and also in terms of parasitics (like gate leakage current) are identified and quantified. This work paves the way to a greater understanding of the device variability in FD-SOI transistors and can be easily adopted to improve the predictability of the commercial SPICE compact models for device variability.

This work builds on a semester project 2. from the winter semester of this academic year. The aim of this thesis is the design of converter using semiconductor components based on SiC technology. This converter is used in the construction of quick charger for electric vehicles. The design of this converter must be based on the requirements for compliance voltage safety. It describes the design of power components used in the construction of this facility, the determination of their losses and determines the overall efficiency of the converter. There is also proposed mathematical model of high-frequency transformer and made his simulation in Matlab-Simulink.

This master’s thesis deals with active electronic loads focusing mostly on alternating input signals. The principles and modes of both DC and AC loads are described, as well as the most important parameters of MOSFET transistor which is used as the main power component. It deals with designing a regulation circuit of an AC load in detail. This work also discusses the possibilities of realisation of the remaining parts of the device. At the end of the thesis the function of the designed regulation circuit is verified by simple measurements on a prototype.

Le défi de la transition vers une énergie sans carbone passe, aujourd’hui, par un recours systématique à l’énergie électrique avec au centre des échanges l’électronique de puissance. Pour être à la hauteur des enjeux, l'électronique de puissance nécessite des composants de plusen plus performants pour permettre un haut niveau d'intégration, une haute efficacité énergétique et un haut niveau de fiabilité. Aujourd’hui, le transistor de puissance, du type MOSFET, en carbure de silicium (SiC) est une technologie de rupture permettant de répondre aux enjeux d’intégration et d’efficacité par un faible niveau de perte et une vitesse de commutation élevée. Cependant, leur fiabilité non maitrisée et leur faible robustesse aux régimes extrêmes du type court-circuit répétitifs freinent aujourd’hui leur pénétration dans les applications industrielles. Dans cette thèse, une étude poussée du comportement en court-circuit d'un ensemble exhaustif de composants commerciaux, décrivant toutes les variantes structurelles et technologiques en jeu, a été menée sur un banc de test spécifique développé durant la thèse, afin de quantifier leur tenue au courtcircuit. Cette étude a mis en lumière des propriétés à la fois génériques et singulières aux semiconducteurs en SiC déclinés en version MOSFET tel qu’un courant de fuite dynamique de grille et un mode de défaillance par un court-circuit grille-source amenant, dans certaines conditions d'usage et pour certaines structures de MOSFET, à un auto-blocage drain-source. Une recherchesystématique de la compréhension physique des phénomènes observés a été menée par une approche mêlant analyse technologique interne des composants défaillants et modélisation électrothermique fine. Une modélisation électrothermique compacte étendue à la prise en compte des modes de défaillance a été établie et implémentée dans un logiciel de type circuit. Ce modèle a été confronté à de très nombreux résultats expérimentaux sur toutes les séquences temporelles décrivant un cycle de court-circuit jusqu'à la défaillance. Ce modèle offre un support d'analyse intéressant et aussi une aide à la conception des circuits de protection. Ainsi, à titre d'application, un driver doté d'une partie de traitement numérique a été conçu et validé en mode de détection de plusieurs scénarii de court-circuit mais aussi potentiellement pour la détection de la dégradation de la grille du composant de puissance. D’autres travaux plus exploratoires ont aussi été menés en partenariat avec l’Université de Nottingham afin d’étudier l'impact de régimes de court-circuit impulsionnels répétés sur le vieillissement de puces en parallèle présentant des dispersions. La propagation d'un premier mode de défaillance issu d'un composant "faible" a aussi été étudiée. Ce travail ouvre la voie à la conception de convertisseurs intrinsèquement sûrs et disponibles en tirant parti des propriétés atypiques et originales des semi-conducteurs en SiC et du MOSFET en particulier / Nowaday, the challenge of the transition to carbon-free energy involves a systematic use of electrical energy with power electronics at the heart of the exchanges. To meet the challenges, power electronics requires increasingly high-performance devices to provide a high level of integration, high efficiency and a high level of reliability. Today, the power transistor, of the MOSFET type, made of silicon carbide (SiC) is a breakthrough technology that allows us to meet the challenges of integration and efficiency through their low level of loss and high switching speed. However, their limited reliability and low robustness at extreme operating conditions such as repetitive short-circuits are now hindering their expansion in industrial applications. In this thesis, an in-depth study of the short-circuit behaviour of an exhaustive set of commercial devices, describing all the structural and technological variants involved, was carried out on a specific test bench developed during the thesis, in order to quantify their short-circuit resistance. This study highlighted both generic and singular properties of SiC semiconductors for every Mosfet version such as a dynamic gate leakage current and a failure mode by a short-circuit grid-source leading, under certain conditions of use and for certain Mosfet structures, to a self-blocking drain-source. A systematic research of the physical understanding of the observed mechanisms was carried out by an approach combining an internal technological analysis of the failed devices and a fine electrothermal modelling. A compact electrothermal modeling extended to failure mode consideration has been established and implemented in circuit software. This model was confronted with numerous experimental results describing a short-circuit cycle up to failure. This model offers an interesting analytical support and also helps the design of protection circuits. Thus, as an application, a driver equipped with a digital processing part has been designed and validated in detection mode for several short-circuit scenarios but also potentially for the detection of the degradation of the power component grid. Other more exploratory work has also been carried out in partnership with the University of Nottingham to study the impact of repeated pulse short-circuit regimes on the aging of parallel chips with dispersions. The propagation of a first failure mode from a "weak" device was also studied. This work paves the way for the design of intrinsically safe and available converters by taking advantage of the atypical and original properties of SiC semiconductors and Mosfet in particular

Efficient power conversion is essential to face the continuously increasing energy consumption of our society. GaN based vertical power field effect transistors provide excellent performance figures for power-conversion switches, due to their capability of handling high voltages and current densities with very low area consumption. This work focuses on a vertical trench gate metal oxide semiconductor field effect transistor (MOSFET) with conceptional advantages in a device fabrication preceded GaN epitaxy and enhancement mode characteristics. The functional layer stack comprises from the bottom an n+/n- drift/p body/n+ source GaN layer sequence. Special attention is paid to the Mg doping of the p-GaN body layer, which is a complex topic by itself. Hydrogen passivation of magnesium plays an essential role, since only the active (hydrogen-free) Mg concentration determines the threshold voltage of the MOSFET and the blocking capability of the body diode. Fabrication specific challenges of the concept are related to the complex integration, formation of ohmic contacts to the functional layers, the specific implementation and processing scheme of the gate trench module and the lateral edge termination. The maximum electric field, which was achieved in the pn- junction of the body diode of the MOSFET is estimated to be around 2.1 MV/cm. From double-sweep transfer measurements with relatively small hysteresis, steep subthreshold slope and a threshold voltage of 3 - 4 V a reasonably good Al2O3/GaN interface quality is indicated. In the conductive state a channel mobility of around 80 - 100 cm2/Vs is estimated. This obtained value is comparable to device with additional overgrowth of the channel. Further enhancement of the OFF-state and ON-state characteristics is expected for optimization of the device termination and the high-k/GaN interface of the vertical trench gate, respectively. From the obtained results and dependencies key figures of an area efficient and competitive device design with thick drift layer is extrapolated. Finally, an outlook is given and advancement possibilities as well as technological limits are discussed.:1 Motivation and boundary conditions 1.1 A comparison of competitive semiconductor materials 1.2 Vertical GaN device concepts 1.3 Target application for power switches 2 The vertical GaN MOSFET concept 2.1 Incomplete ionization of dopants 2.2 The pseudo-vertical approach 2.3 Considerations for the device OFF-state 2.3.1 The pn-junction in reverse operation 2.3.2 The gate trench MIS-structure in OFF-state 2.3.3 Dimensional constraints and field plates 2.4 Static ON-state and switching considerations 2.4.1 The pn-junction in forward operation 2.4.2 Resistance contributions 2.4.3 Device model and channel mobility 2.4.4 Threshold voltage and subthreshold slope 2.4.5 Interface and dielectric trap states in wide band semiconductors 2.4.6 The body bias effect 3 Fabrication and characterisation 3.1 Growth methods for GaN substrates and layers 3.2 Substrates and the desired starting material 3.2.1 Physical and micro-structural characterisation 3.2.2 Dislocations and impurities 3.3 Pseudo- and true-vertical MOSFET fabrication 3.3.1 Processing routes 3.3.2 Inductively-coupled plasma etching 3.3.3 Process flow modification 3.4 Electrical characterisation, structures and process control 3.4.1 Current voltage characterisation 3.4.2 C(V) measurements and charge carrier profiling 3.4.3 Cooperative characterisation structures 4 Properties of the functional layers 4.1 Morphology of the MOVPE grown layers 4.2 Hydrogen out-diffusion treatment 4.3 Morphology of the n+-source layer grown by MBE 4.4 N-type doping of the functional layers 4.5 P-type GaN by magnesium doping 4.6 Structural properties after the etching and gate module formation 4.7 Electrical layer characterization 4.7.1 Gate dielectric and interface evaluation 5 Pseudo- and true vertical device operation 5.1 Influences of the metal-line sheet resistance 5.2 Formation and characterisation of ohmic contacts 5.2.1 Ohmic contacts to n-type GaN 5.2.2 Ohmic contacts to p-GaN 5.3 The pn- body diode 5.4 MOSFET operation 5.4.1 ON-state and turn-ON operation 5.4.2 The body bias effect on the threshold voltage 5.4.3 Device OFF-state 6 Summary and conclusion 6.1 Device performance 6.2 Current limits of the vertical device technology 6.3 Possibilities for advancements Bibliography A Appendix A.1 Deduction: Forward diffusion current of the pn-diode A.2 Deduction: Operation regions in the EKV model Figures Tables Abbreviations Symbols Postamble and Acknowledgement

Les travaux de recherche présentés dans ce mémoire, portent sur la conception et l’étude de MOSFETs de puissance faible tension pour des applications automobiles micro-hybrides de type alterno-démarreur. Pour certaines de ces applications, en plus des modes de fonctionnement standards passant et bloqué, les composants développés doivent être capables de fonctionner en mode d’avalanche à fort courant et à des températures élevées. Pour reproduire en laboratoire ces conditions de fonctionnement, les MOSFETs sont soumis à un test UIS répétitif spécifique. Afin d’évaluer la température du silicium pendant ce test, plusieurs méthodes de mesure de température ont été développées et comparées. En parallèle, un suivi des paramètres électriques standards (BVDSS, IDSS, RDSon…) tout au long du test est effectué, dans le but de déterminer l’impact de l’avalanche répétitive sur le transistor. Seule la RDSon des MOSFETs semble évoluer avec le nombre d’impulsions d’avalanche. Ce phénomène est expliqué par la méthode de mesure de RDSon et par la variation de la résistance du métal source pendant le cyclage. En effet, différentes observations ont permis de constater un vieillissement de la métallisation de source du composant, accompagné d’une modification de sa résistivité. Divers types de métaux et de techniques d’assemblage ont alors été expérimentés pour tenter de limiter cet effet. Aussi des structures de test ont été conçues pour étudier l’évolution du métal et pour pouvoir comparer rapidement le comportement de différentes métallisations / Research work presented in this thesis concern the conception and the study of low voltage power MOSFETs for micro hybrid vehicles (starter alternator). For some of these applications, developed transistors must be able to operate in classical ON and OFF state mode and in avalanche mode at high current and high temperature. To reproduce this operating mode, MOSFETs are submitted to a specific repetitive UIS test. In order to evaluate silicon’s temperature during this test, several temperature measurement methods have been developed and compared. In parallel, in order to understand the impact of repetitive avalanche on the transistor, standard electrical parameters (BVDSS, IDSS, RDSon…) are monitored during the test. The only parameter that seems to be shifting with the number of cycles is the RDSon. This phenomenon is due to the measurement method and to a variation of source metallization resistance during cycling. Indeed several observations have shown source metallization ageing and a shift in its resistivity. Different metallization and assembly parameters have been tested to limit this phenomenon. Also various test structures have been designed to study metallization evolution and to compare different metallization behaviors

Evolutions in integrated circuit technology require the use of a high-frequency synchronous buck converter in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency operation leads to increased power MOSFET switching losses. Optimization of the MOSFETs plays an important role in improving converter performance. This dissertation focuses on revealing the power loss mechanism of power MOSFETs and the relationship between power MOSFET structure and its power loss. The analytical device model, combined with circuit modeling, cannot reveal the relationship between device structure and its power loss due to the highly non-linear characteristics of power MOSFETs. A physically-based mixed device/circuit modeling approach is used to investigate the power losses of the MOSFETs under different operating conditions. The physically based device model, combined with SPICE-like circuit simulation, provides an expeditious and inexpensive way of evaluating and optimizing circuit and device concepts. Unlike analytical or other SPICE models of power MOSFETs, the numerical device model, relying little on approximations or simplifications, faithfully represents the behavior of realistic power MOSFETs. The impact of power MOSFET parameters on efficiency of synchronous buck converters, such as gate charge, on resistance, reverse recovery, is studied in detail in this thesis. The results provide a good indication on how to optimize power MOSFETs used in VRMs. The synchronous rectifier plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact SyncFET's performance. This thesis gives a detailed analysis of the SyncFET operation mechanism and provides several techniques to reduce its body-diode influence and suppress its false Cdv/dt trigger-n. This thesis also investigates the influence of several circuit level parameters on the efficiency of the synchronous buck converter, such as input voltage, circuit parasitic inductance, and gate resistance to provide further optimization of synchronous buck converter design.

The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs. / M.S. / Recent years, the prosperity of power electronics applications such as electric vehicle and smart grid has led to a rapid increase in the adoption of wide bandgap (WBG) power devices. Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, capability of operation at high temperatures, and superior device robustness over other WBG power devices. In most power converters, power device is required to conduct current in its third quadrant (3rd-quad) (i.e., conduct reverse current) either for handling current during the dead time or acting as a commutation switch. In a SiC MOSFET, there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is widely accepted that by turning on the MOS channel with a positive gate-to-source bias (VGS), both paths are turned on in parallel such that the 3rd-quad conduction loss can be reduced. In this thesis work, it is shown that this long-held opinion does not hold for SiC MOSFETs with high voltage ratings (e.g., 3.3 kV and 10 kV). Through a combination of device characterization, TCAD simulation, and analytical modeling, this thesis work unveils the competing current sharing between the MOS channel and the body diode. Once the MOS channel turns on, it delays the turn-on of the body diode and suppresses the diode current. This effect is more pronounced in MOSFETs with higher voltage ratings. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on in the practical operation conditions. At high temperatures, as the bipolar diode path possesses the conductivity modulation, which can significantly lower the voltage drop and is absent in the MOS channel, it would be optimal to turn off the MOS channel. Circuit test is also performed to validate these device findings and evaluate their impact on device applications. Finally, the study is also extended to the commercial SiC trench MOSFET, the other mainstream type of SiC power MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.

Sur les différents calculateurs du véhicule, de plus en plus d'organes sont commandés par un interrupteur en silicium (circuit MOSFET) au lieu d'un relais. En plus de la fonction de commutation de puissance, le MOSFET peut comprendre un dispositif de mesure du courant afin de contrôler le pilotage de l'organe et/ou assurer une fonction de diagnostic. On appelle ce type de composant un commutateur intelligent de puissance ou Smart Switch. Il est aussi prévu dans le Smart Switch un dispositif de coupure du courant, en cas d'échauffement interne dû à une surintensité électrique. Avec les dernières avancées technologiques, ces composants peuvent aussi intégrer de la logique de pilotage et une interface de liaison numérique avec un microprocesseur. Cette dernière caractéristique motive lesujet de l'étude afin de définir des lois de protection améliorées contre les échauffements dus à une surintensité électrique.En effet, d’un point de vue de la protection électrique, le MOSFET a été conçu pour obtenir les mêmes caractéristiques qu’un fusible, avec la possibilité supplémentaire d’être réenclenché comme un disjoncteur. Le but est d’étudier les lois de pilotage qui pourraient permettre de mieux suivre les limites thermiques d’un conducteur électrique, en particulier dans les faibles surintensités, de façon à pouvoir diminuer le diamètre (donc le coût) des fils tout en assurant une meilleure protection face aux courts circuits impédants (courts-circuits sur une résistance un peu inférieure à la résistance nominale ducircuit, dans un rapport entre 1 et 3 par exemple). / On various vehicles Electronic Control Unit (ECU), more and more members are controlled bya MOSFET circuits instead of a relay. In addition to the power switching function, the MOSFET maymeasure the current to the steering control of the body and / or to ensure that a diagnostic function. Wecall this type of component a smart power switch or Smart Switch. It is also provided in the SmartSwitch device power failure, if the internal heating caused by electrical current. With the latesttechnology, these components can also integrate control logic and an interface for connection to adigital microprocessor. This last characteristic motivates the subject of study in order to defineimproved protection laws against overheating caused by an electrical current.Indeed, from the point of view of electrical protection, the MOSFET has been designed toachieve the same characteristics as a fuse, with the additional possibility to be reset as a circuit breaker.The aim is to study the control laws that could lead to better monitor the thermal limits of an electricalconductor, especially in low current, so as to reduce the diameter (hence the cost) of son while ensuringbetter protection against short-circuit-impedance (short circuit resistance of a little less than thenominal resistance of the circuit, in a ratio between 1 and 3 for example).