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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.


DUTTA, MADHULIKA 07 July 2003 (has links)
No description available.

A Scalable Architecture for Massive MIMO Base Stations Using Distributed Processing

Bertilsson, Erik January 2017 (has links)
Massive MIMO is an emerging technology for future wireless systems that has received much attention from both academia and industry recently. The most prominent feature of Massive MIMO is that the base station is equiped with a large number of antennas. It is therefore important to create scalable architectures to enable simple deployment in different configurations. In this thesis, a distributed architecture for performing the baseband processing in a massive OFDM MU-MIMO system is proposed and analyzed. The proposed architecture is based on connecting several identical nodes in a K-ary tree. It is shown that, depending on the chosen algorithms, all or most computations can be performed in a distrbuted manner. Also, the computational load of each node does not depend on the number of nodes in the tree (except for some timing issues) which implies simple scalability of the system. It is shown that it should be enough that each node contains one or two complex multipliers and a few complex adders running at a couple of hundres MHz to support specifications similar to LTE. Additionally the nodes must communicate with each other over links with data rates in the order of some Gbps. Finally, a VHDL implementation of the system is proposed. The implementation is parameterized such that a system can be generated from a given specification.

B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC / B-ASIC - Better ASIC Toolbox : A toolbox that simplifies ASIC design and optimization

Lothian, Angus, Härnqvist, Ivar, Jakobsson, Adam, Westerlund, Arvid, Goding, Felix, Wahlman, Jacob, Scott, Kevin, Karlsson, Rasmus January 2020 (has links)
Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte var att utveckla en verktygslåda i Python och C++ för att konstruera signalbehandlade kretsar. Denna verktygslåda är tänkt att användas inom laborationer i kursen TSTE87 Applikationsspecfika integrerande kretsar vid Linköpings universitet och inom forskning för utveckling av ASIC:s. Projektet resulterade i produkten B-ASIC. B-ASIC är ett bibliotek för programmeringsspråket Python som är skrivet i Python med en underliggande modul i C++. B-ASIC används för design och optimering av ASIC:s. Produkten B-ASIC erbjuder ett grafiskt användargränssnitt där användaren kan interagera med biblioteket utan programmeringskunskaper inom Python. I rapporten beskrivs hur projektarbetet har anpassats för att vara till värde för kunden och hur utvecklingsprocessen har påverkat resultatet av produkten. Projektmedlemmarna har dessutom genomfört egna undersökningar och dessa finns att läsa i slutet av rapporten.

Méthodologie de prédiction multi-échelle pour l'évaluation et le durcissement des circuits intégrés complexes face aux événements singuliers d'origine radiative / Multi-scale prediction methodology of ASIC sensitivity to radiation induced single event effects and its hardening

Andrianjohany, Nomena Gabriel 02 March 2018 (has links)
La forte densité d'intégration et la miniaturisation des composants électroniques les rendent de plus en plus sensibles aux effets singuliers. Cette sensibilité est observée dans des environnements déjà largement étudiés (spatial, nucléaire) mais commence à apparaître au niveau du sol pour des applications grand public jusqu'à maintenant épargnées par de tels effets. Il devient ainsi indispensable pour les concepteurs et les fabricants de composants électroniques complexes (ASIC) de prédire la sensibilité de nouveaux composants ou de nouvelles technologies dès la phase de conception sans avoir besoin de les fabriquer.Cette thèse vise à élaborer une méthodologie de prédiction pour l'évaluation et le durcissement de ces circuits intégrés complexes face aux événements singuliers dans le but d'évaluer leur fiabilité avant la fabrication et ainsi réduire le coût des tests. Les phases de l'étude consistent à i) analyser le lien entre modèle physique et défaillance au niveau macroscopique afin de proposer des chaînes de prédiction, ii) mettre en œuvre les chaînes et valider les modèles associés sur des structures simples iii) appliquer et valider les méthodes de prédiction sur un cas réel de conception. / The scaling trend of highly integrated circuits makes them more and more sensitive to single event effects (SEE). This sensitivity was observed in widely studied environments (spatial, nuclear) but also in general public applications up to now spared by such effects. It has now become necessary for circuit designers to estimate the sensitivity of their circuit and new technology during the design phase and thus avoid spending efforts on unnecessary circuit manufacturing and testing.This thesis aims to develop a prediction methodology for integrated circuits evaluation and hardening face to the single event effect in order to assess their reliability before manufacturing and therefore, reduce the testing costs. The first step of the study is the analysis of the link between physical model and macroscopic failure in order establish prediction chains. The second step is the implementation of these chains and the validation of the associated models using simple circuits. The final step is the application and the validation of the prediction methods within a real integrated circuit design flow.

Multiple personality integrated circuits and the cost of programmability

York, Johnathan Andrew 11 July 2012 (has links)
This dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication technology. The central claim elevates programmability to an explicit design parameter that (1) can be rigorously defined, (2) has measurable costs amenable to high-level modeling, (3) yields a design-space with distinct regions and properties, and (4) can be usefully manipulated using computer-aided design tools. The first portion of the the work is devoted to laying a rigorous logical foundation to support both this and future work on the subject. The second portion supports the thesis within this established logical foundation, using a specific engineering problem as a narrative vehicle. The engineering problem explored is that of mechanically adding a useful degree of programmability into preexisting fixed-function logic while minimizing the added overhead. Varying criteria for usefulness are proposed and the relative costs estimated both analytically and through case-study using standard-cell logic synthesis. In the case study, a methodology for the automatic generation of reconfigurable logic highly optimized for a specific set of computing applications is demonstrated. The approach stands in contrast to traditional reconfigurable computing techniques which focus on providing general purpose functionality at the expense of substantial overheads relative to fixed-purpose implementations. / text

3D graphics hardware prototyping and implementation

Ford, Nicky January 2000 (has links)
No description available.

High Speed Vlsi Implementation Of The Rijndael Encryption Algorithm

Sever, Refik 01 January 2003 (has links) (PDF)
This thesis study presents a high speed VLSI implementation of the Rijndael Encryption Algorithm, which is selected to be the new Advanced Encryption Standard (AES) Algorithm. Both the encryption and the decryption algorithms of Rijndael are implemented as a single ASIC. Although data size is fixed to 128 bits in the AES, our implementation supports all the data sizes of the original Rijndael Algorithm. The core is optimised for both area and speed. Using 149K gates in a 0.35-&micro / m standard CMOS process, 132 MHz worst-case clock speed is achieved yielding 2.41 Gbit/s non-pipelined throughput in both encryption and decryption. iii The design has a latency of 30 clock periods for key expansion that takes 228 ns for this implementation. A single encryption or decryption of a data block requires at most 44 clock periods. The area of the chip is 12.8 mm2 including the pads. 0.35-&micro / m Standard Cell Libraries of the AMI Semiconductor Company are used in the implementation. The literature survey revealed that this implementation is the fastest published non-pipelined implementation for both encryption and decryption algorithms.

Study of Interferer Canceling Systems in a Software Defined Radio Receiver / Studie av Störsignalsneutraliserande System i en Mjukvarudefinierad Radiomottagare

Holstensson, Oskar January 2013 (has links)
This thesis describes the work related to an interferer rejection system employing frequency analysis and cancellation through phase-opposed signal injection. The first device in the frequency analysis chain, an analog fast Fourier transform application-specific integrated circuit (ASIC), was improved upon. The second device, a chained fast Fourier transform followed by a frequency analysis module employing cross-correlation for signal detection was specified, designed and implemented in VHDL.

Low Power Design Using RNS

Classon, Viktor January 2014 (has links)
Power dissipation has become one of the major limiting factors in the design of digital ASICs. Low power dissipation will increase the mobility of the ASIC by reducing the system cost, size and weight. DSP blocks are a major source of power dissipation in modern ASICs. The residue number system (RNS) has, for a long time, been proposed as an alternative to the regular two's complement number system (TCS) in DSP applications to reduce the power dissipation. The basic concept of RNS is to first encode the input data into several smaller independent residues. The computational operations are then performed in parallel and the results are eventually decoded back to the original number system. Due to the inherent parallelism of the residue arithmetics, hardware implementation results in multiple smaller design units. Therefore an RNS design requires low leakage power cells and will result in a lower switching activity. The residue number system has been analyzed by first investigating different implementations of RNS adders and multipliers (which are the basic arithmetic functions in a DSP system) and then deriving an optimal combination of these. The optimum combinations have been used to implement an FIR filter in RNS that has been compared with a TCS FIR filter. By providing different input data and coefficients to both the RNS and TCS FIR filter an evaluation of their respective performance in terms of area, power and operating frequency have been performed. The result is promising for uniform distributed random input data with approximately 15 % reduction of average power with RNS compared to TCS. For a realistic DSP application with normally distributed input data, the power reduction is negligible for practical purposes.

Cryptoraptor : high throughput reconfigurable cryptographic processor for symmetric key encryption and cryptographic hash functions

Sayilar, Gokhan 03 February 2015 (has links)
In cryptographic processor design, the selection of functional primitives and connection structures between these primitives are extremely crucial to maximize throughput and flexibility. Hence, detailed analysis on the specifications and requirements of existing crypto-systems plays a crucial role in cryptographic processor design. This thesis provides the most comprehensive literature review that we are aware of on the widest range of existing cryptographic algorithms, their specifications, requirements, and hardware structures. In the light of this analysis, it also describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, that is designed to support both today's and tomorrow's encryption standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor targeting the future standards as well. Unlike previous work, we aim for maximum throughput for all known encryption standards, and to support future standards as well. Our 1GHz design achieves a peak throughput of 128Gbps for AES-128 which is competitive with ASIC designs and has 25X and 160X higher throughput per area than CPU and GPU solutions, respectively. / text

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