Processadores embarcados utilizam eficientemente o paralelismo a nível de instrução para atender as necessidades de desempenho e energia em aplicações atuais. Embora a melhoria de performance seja um dos principais objetivos em processadores em geral, ela pode levar a um impacto negativo no consumo de energia, uma restrição crítica para sistemas atuais. Nesta dissertação, apresentamos o SoMMA, uma arquitetura de memória gerenciada por software para processadores embarcados capaz de reduz consumo de energia e energy-delay product (EDP), enquanto ainda aumenta a banda de memória. A solução combina o uso de memórias gerenciadas por software com a cache de dados, de modo a reduzir o consumo de energia e EDP do sistema. SoMMA também melhora a performance do sistema, pois os acessos à memória podem ser realizados em paralelo, sem custo em portas de memória extra na cache de dados. Transformações de código do compilador auxiliam o programador a utilizar a arquitetura proposta. Resultados experimentais mostram que SoMMA é mais eficiente em termos de energia e desempenho tanto a nível de processador quanto a nível do sistema completo. A técnica apresenta speedups de 1.118x e 1.121x, consumindo 11% e 12.8% menos energia quando comparando processadores que utilizam e não utilizam SoMMA. Há ainda redução de até 41.5% em EDP do sistema, sempre mantendo a área dos processadores equivalentes. Por fim, SoMMA também reduz o número de cache misses quando comparado ao processador baseline. / Embedded processors rely on the efficient use of instruction-level parallelism to answer the performance and energy needs of modern applications. Though improving performance is the primary goal for processors in general, it might lead to a negative impact on energy consumption, a particularly critical constraint for current systems. In this dissertation, we present SoMMA, a software-managed memory architecture for embedded multi-issue processors that can reduce energy consumption and energy-delay product (EDP), while still providing an increase in memory bandwidth. We combine the use of software-managed memories (SMM) with the data cache, and leverage the lower energy access cost of SMMs to provide a processor with reduced energy consumption and EDP. SoMMA also provides a better overall performance, as memory accesses can be performed in parallel, with no cost in extra memory ports. Compiler-automated code transformations minimize the programmer’s effort to benefit from the proposed architecture. Our experimental results show that SoMMA is more energy- and performance-efficient not only for the processing cores, but also at full-system level. Comparisons were done using the VEX processor, a VLIW reconfigurable processor. The approach shows average speedups of 1.118x and 1.121x, while consuming up to 11% and 12.8% less energy when comparing two modified processors and their baselines. SoMMA also shows reduction of up to 41.5% on full-system EDP, maintaining the same processor area as baseline processors. Lastly, even with SoMMA halving the data cache size, we still reduce the number of data cache misses in comparison to baselines.

In this thesis we study two discrete optimization problems: Traffic Light Synchronization and Location with Customers Orderings. A widely used approach to solve the synchronization of traffic lights on transport networks is the maximization of the time during which cars start at one end of a street and can go to the other without stopping for a red light (bandwidth maximization). The mixed integer linear model found in the literature, named MAXBAND, can be solved by optimization solvers only for small instances. In this manuscript we review in detail all the constraints of the original linear model, including those that describe all the cyclic routes in the graph, and we generalize some bounds for integer variables which so far had been presented only for problems that do not consider cycles. Furthermore, we summarized the first systematic algorithm to solve a simpler version of the problem on a single street. We also propose a solution algorithm that uses Tabu Search and Variable Neighbourhood Search and we carry out a computational study. In addition we propose a linear formulation for the shortest path problem with traffic lights constraints (SPTL). On the other hand, the simple plant location problem with order (SPLPO) is a variant of the simple plant location problem (SPLP) where the customers have preferences on the facilities which will serve them. In particular, customers define their preferences by ranking each of the potential facilities. Even though the SPLP has been widely studied in the literature, the SPLPO has been studied much less and the size of the instances that can be solved is very limited. In this manuscript, we propose a heuristic that uses a Lagrangean relaxation output as a starting point of a semi-Lagrangean relaxation algorithm to find good feasible solutions (often the optimal solution). We also carry out a computational study to illustrate the good performance of our method. Last, we introduce the partial and stochastic versions of SPLPO and apply the Lagrangean algorithm proposed for the deterministic case to then show examples and results.

Submitted by Lara Oliveira (lara@ufersa.edu.br) on 2017-05-24T22:06:39Z No. of bitstreams: 1 AnamariaSM_DISSERT.pdf: 10659120 bytes, checksum: 007308f84bbdb900c2823d1a72b2f4a4 (MD5) / Approved for entry into archive by Vanessa Christiane (referencia@ufersa.edu.br) on 2017-05-26T11:53:10Z (GMT) No. of bitstreams: 1 AnamariaSM_DISSERT.pdf: 10659120 bytes, checksum: 007308f84bbdb900c2823d1a72b2f4a4 (MD5) / Approved for entry into archive by Vanessa Christiane (referencia@ufersa.edu.br) on 2017-05-26T11:54:09Z (GMT) No. of bitstreams: 1 AnamariaSM_DISSERT.pdf: 10659120 bytes, checksum: 007308f84bbdb900c2823d1a72b2f4a4 (MD5) / Made available in DSpace on 2017-05-26T11:54:39Z (GMT). No. of bitstreams: 1 AnamariaSM_DISSERT.pdf: 10659120 bytes, checksum: 007308f84bbdb900c2823d1a72b2f4a4 (MD5) Previous issue date: 2016-05-19 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Communication systems it has excelled in the development, social, economic and cultural society. Every time there are new technologies seeking to offer the fastest, easy and reliable access to various communications services. In this context, the microstrip antennas stand out by having compact size and reduced cost. However, it presents some limitations related to narrow bandwidth and low gain. A significant advance to minimize these losses came to the use of structures EBG (Electromagnetic Band Gap) and PBG (Photonic Band Gap) in the components of the antennas. This paper proposes the study and analysis of the behavior of microstrip antennas properties designed with EBG/PBG structures in the substrate and the ground plane. So that the structures are arranged just under the patch and are developed with variations in radius, cylinder height and positioning in the ground plane. For the resonance frequency 5.85 GHz, and substrates of different permittivity. In computer modeling was used ANSYS HFFS® software. After analyzing the simulated results seven devices were built, through a vector network analyzer, the measurements of the main parameters were performed. Ultimately simulation are compared and measured values, so that the results presented in most configurations a concord in the pattern of graphics, although the frequency displacement. Also noted that antennas with the EBG/PBG structures presented multiband, enabling the application specific frequency bands as well as, an increase in the value of total gain, bandwidth and reduction of surface currents / Os sistemas de comunicação assumiram papéis fundamentais para o desenvolvimento, social, econômico e cultural na sociedade. A cada momento, surgem novas tecnologias procurando oferecer o acesso mais rápido, fácil e confiável aos diversos serviços de comunicações. Nesse contexto, as antenas de microfita se destacam por possuírem características como, tamanho compacto e custo reduzido. No entanto, apresentam algumas limitações relacionadas a largura de banda estreita e ganho reduzido. Um avanço significativo para minimizar essas perdas, proveio com a utilização de estruturas de bandas proibidas (EBG – Eletromagnetic Band Gap e PBG – Photonic Band Gap) nos componentes das antenas. Este trabalho propõe o estudo e análise do comportamento das propriedades de antenas de microfita projetadas com configurações de estruturas EBG/PBG no substrato e no plano de terra. De modo que as estruturas estão arranjadas apenas sob o patch e, são desenvolvidas com variações no raio, altura do cilindro e posicionamento no plano de terra. Para a frequência de ressonância de 5,85 GHz, e substratos de diferentes permissividades. Na modelagem computacional foi utilizado o software ANSYS HFFS®, e com a análise dos resultados simulados foram fabricados sete dispositivos, onde através de um analisador de redes vetoriais, foram realizadas as medições dos principais parâmetros. Por fim são comparados os valores simulados e medidos, de modo que que os resultados apresentaram na maioria das configurações uma concordância no padrão de seus gráficos, apesar dos deslocamentos de frequência. Também foi observado que as antenas com as estruturas EBG/PBG apresentaram comportamento de multibandas, possibilitando a aplicação em faixas de frequências específicas, assim como, ocorreu um aumento nos valores de ganho total, largura de banda e a redução das correntes de superfície / 2017-05-24

The beginning of the 21 st century is characterised, among others, by the evolution in telecommunications. The rapid growth of mobile communications and the variety of applications proposed for the third generation (3G) systems require long operation time, low weight and cost for terminals, as well as improved link quality. For this reason a good efficiency and low profile antennas with low absorption losses by the user are desirable. The Planar Inverted-F Antenna (PIFA) is shown to result into low SAR values and high efficiency when operating in the proximity of the user. Despite these advantages, PIFA is also characterised by narrow bandwidth that limits its practical use. The first part of this work is dedicated to the measurements and evaluation of the radiation characteristics of the PIFA and other wire antennas both in the near and far fields. In addition, novel methods of PIFA tuning are presented. These include the repositioning of the shorting pin and modification of its capacitance. By using these techniques, the effective bandwidth of the PIFA can be increased to satisfy the GSM900 and DCS 1800 system bandwidth requirements. Dual-band and electronically tuned PIFA prototypes are also included. The effects of the handset size on the mass averaged Specific Absorption Rate (SAR), and antenna efficiency are investigated. The appropriate choice of handset can result in up to 30%-reduced peak SAR. The computed SAR values from PIFA are compared with those resulting from the use of a handset equipped with quarter wavelength monopole antenna. A new measure referred to as the 3dB SAR volume is proposed. This measure provides better understanding of the absorbed power distribution in the operator's head. Results obtained in the course of study show that low profile handset antennas, such as the PIFA, present in addition to dual resonance and low reflection losses, reduced SAR values, high efficiency and low 3dB SAR volume. Finally, SAR and 3dB SAR volume values from simulations on 5- and 10- years old child head models are compared with their equivalents for adult models from which appropriate conclusions are drawn.

Processadores embarcados utilizam eficientemente o paralelismo a nível de instrução para atender as necessidades de desempenho e energia em aplicações atuais. Embora a melhoria de performance seja um dos principais objetivos em processadores em geral, ela pode levar a um impacto negativo no consumo de energia, uma restrição crítica para sistemas atuais. Nesta dissertação, apresentamos o SoMMA, uma arquitetura de memória gerenciada por software para processadores embarcados capaz de reduz consumo de energia e energy-delay product (EDP), enquanto ainda aumenta a banda de memória. A solução combina o uso de memórias gerenciadas por software com a cache de dados, de modo a reduzir o consumo de energia e EDP do sistema. SoMMA também melhora a performance do sistema, pois os acessos à memória podem ser realizados em paralelo, sem custo em portas de memória extra na cache de dados. Transformações de código do compilador auxiliam o programador a utilizar a arquitetura proposta. Resultados experimentais mostram que SoMMA é mais eficiente em termos de energia e desempenho tanto a nível de processador quanto a nível do sistema completo. A técnica apresenta speedups de 1.118x e 1.121x, consumindo 11% e 12.8% menos energia quando comparando processadores que utilizam e não utilizam SoMMA. Há ainda redução de até 41.5% em EDP do sistema, sempre mantendo a área dos processadores equivalentes. Por fim, SoMMA também reduz o número de cache misses quando comparado ao processador baseline. / Embedded processors rely on the efficient use of instruction-level parallelism to answer the performance and energy needs of modern applications. Though improving performance is the primary goal for processors in general, it might lead to a negative impact on energy consumption, a particularly critical constraint for current systems. In this dissertation, we present SoMMA, a software-managed memory architecture for embedded multi-issue processors that can reduce energy consumption and energy-delay product (EDP), while still providing an increase in memory bandwidth. We combine the use of software-managed memories (SMM) with the data cache, and leverage the lower energy access cost of SMMs to provide a processor with reduced energy consumption and EDP. SoMMA also provides a better overall performance, as memory accesses can be performed in parallel, with no cost in extra memory ports. Compiler-automated code transformations minimize the programmer’s effort to benefit from the proposed architecture. Our experimental results show that SoMMA is more energy- and performance-efficient not only for the processing cores, but also at full-system level. Comparisons were done using the VEX processor, a VLIW reconfigurable processor. The approach shows average speedups of 1.118x and 1.121x, while consuming up to 11% and 12.8% less energy when comparing two modified processors and their baselines. SoMMA also shows reduction of up to 41.5% on full-system EDP, maintaining the same processor area as baseline processors. Lastly, even with SoMMA halving the data cache size, we still reduce the number of data cache misses in comparison to baselines.

Detta arbete undersöker synkroniseringstekniken dead reckoning i racingspel. Mer specifikt hur en variant, där objekts avstånd från varandra dynamiskt kontrollerar hur ofta de synkroniseras över nätverket, presterar gällande bandbreddsåtgång och konsistens jämfört med vanlig dead reckoning som alltid synkroniserar lika ofta. Det undersöks också hur banornas karaktär och egenskaper påverkar resultatet. Det visar sig att denna dynamiska dead reckoning har god potential att ge förbättringar gällande bandbreddsåtgång och att banornas utformning har stor inverkan över hur stor denna potential är.

This thesis describes theoretic proposal and two practical realization of multi - point wireless network, first for communications between two endpoints and second for wireless signal coverage of a structured space. The wireless network is realized by the equipment working in unlicenced 2,4GHz and 5GHz ISM band. The wireless device are configured in three different wireless mods: WDS, WDS bridge and AP. This paper contains short information about IEEE 802.11a/b/g/n standard and associated proprietary wireless specifications. Practical workshop describes several variants connections and present the result of throughtput measurements, depending on wireless network topology.

O aumento da demanda por sistemas computacionais mais eficientes para obter alto desempenho impôs novos desafios à comunidade de pesquisa, que precisou buscar por novas plataformas heterogêneas para grandes aplicações. Para utilizar todo o potencial dessas plataformas, podese agrupar a aplicação em grupos menores de modo que cada grupo seja executado em uma unidade de processamento específica, para reduzir o gargalo de comunicação, de acordo com o comportamento de comunicação durante a execução da aplicação. Com o propósito de oferecer um agrupamento mais eficiente, este projeto propõe a análise de agrupamento de uma aplicação levando em consideração não só o volume total de dados, mas também a distribuição desse volume durante o tempo de execução associado à restrição da banda e da taxa de transmissão. Embora alguns trabalhos considerem o volume total de dados para o agrupamento, não é evidenciado como esse volume é distribuído e como a restrição de banda afeta o agrupamento. Assim, neste projeto foi implementado um framework para sugerir um agrupamento considerando a distribuição do volume de comunicação e restrições de banda. Além disso, foi desenvolvido um módulo de extensão para a ferramenta externa MCProf (Memory and Communication Profiler) com o objetivo de obter a distribuição do volume de comunicação. A validação do framework foi realizada por meios de testes de agrupamentos de aplicações nos quais foram comparados o tempo de comunicação do agrupamento gerado pela execução do framework em relação aos resultado dos agrupamentos considerando os trabalhos da literatura. O uso desta abordagem apresentou um aumento no desempenho que variou de 1,117X a 2,621X para as aplicações usadas nos experimentos. / The increased demand for more efficient computing systems to achieve high performance proposed new challenges to the research community, which needed to search for new heterogeneous platforms for large applications. To utilize the full potential of these platforms, the application can be grouped into small groups that runs on a specific processing unit to reduce the communication bottleneck according to the communication behavior during application execution . With the purpose of offering a more efficient clustering, this project proposes the analysis of clustering of an application taking into account not only the total volume of data, but also the distribution of that volume during the execution time associated to the band and restriction of rate transmission. Although some studies consider the total volume of data for the cluster, it is not clear how this volume is distributed and how the band constraint affects clustering. Thus, in this project was implemented a framework to suggest a cluster considering the distribution of the volume of communication and band restrictions. In addition, an extension module was developed for the external tool MCProf (Memory and Communication Profiler) in order to obtain the distribution of the communication. The validation of the framework was performed by clsutering tests which used applications in which the communication time of the cluster generated by the execution of framework was compared to the results of the clusters considering the literature. The use of this approach showed an increase in performance ranging from 1.117X to 2.621X for the applications used in the experiments.

Covert Channels have existed for more than twenty years now. Although they did not receive a special attention in their early years, they are being more and more studied nowadays. This work focuses on network covert channels and it attempts to give an overview on their basics to later analyse several existing implementations which may compromise the security perimeter of a corporate network. The features under study are the bandwidth provided by the channel and the ease of detection. The studied tools have turned out to be in most cases unreliable and easy to detect with current detection techniques and the bandwidth provided is usually moderate but they might pose a threat if not taken into consideration.

Un Convertisseur Analogique-Numérique (CAN) pour les applications spatiales en astrophysique et cosmologie a été développé au cours de cette thèse. Cette catégorie de circuits demande des bandes passantes très larges, de très hautes fréquences d'échantillonnage et une faible résolution. L’architecture flash a été retenue pour sa rapidité et sa bande passante. La fréquence d’échantillonnage est de 8GHz. La technologie utilisée est la CMOS 65 nm de chez STMicroeletronics. La conception a été faite en deux phases. Une première qui a amené à un prototype d'un échantillonneur-bloqueur et une deuxième qui a amené au CAN. Les deux prototypes ont été caractérisés et à partir de ces résultats des perspectives d'amélioration pour les nouvelles implémentations ont été retrouvées.Pour atteindre l'objectif final du CAN multi-bits (6-bit sont visés) il a été décidé de dessiner une première version du CAN avec la moitié de la résolution initialement prévue (on passe de 6-bit à 3-bit). L'objectif est de nous permettre d’analyser le comportement des blocs fonctionnels intégrés et ensuite passer à une deuxième voire troisième version pour remplir le cahier des charges initial. / An Analog-to-Digital Converter (ADC) has been developed for astrophysical and cosmological applications. This class of circuits demands, especially in the millimeter wavelength domain, ultra wide bandwidths, ultra high sampling frequencies and a low resolution. The “flash” architecture has been chosen for its speed and bandwidth. This ADC samples at 8Gsps and it has been fabricated in 65nm CMOS technology from STMicroelectornics.The design has been done in two steps. The first was the prototype of a track-and-hold circuit. The second was the ADC. Both circuits have been characterized and from these results some perspectives for further improvements have been proposed.In order to achieve the final goal of the multi-bit ADC (6-bit resolution) we have decided to design a first prototype with half the final resolution, namely a 3-bit resolution ADC. Our idea was, with this first prototype, to conduct a first analysis of the behavior of the integrated functional blocks and, consequently, find the correct improvements required for the ADC final version.