Sistemas baseados em processadores de uso geral caracterizam-se pela flexibilidade a mudanças de projeto, porém com desempenho computacional abaixo daqueles baseados em circuitos dedicados otimizados. A implementação de algoritmos em dispositivos reconfiguráveis, conhecidos como Field Programmable Gate Arrays - FPGAs, oferece uma solução de compromisso entre a flexibilidade dos processadores e o desempenho dos circuitos dedicados, pois as FPGAs permitem que seus recursos de hardware sejam configurados por software, com uma granularidade menor que a do processador de uso geral e flexibilidade maior que a dos circuitos dedicados. As versões atuais de FPGAs apresentam um tempo de reconfiguração suficientemente pequeno para viabilizar sua reconfiguração dinâmica, i.e., mesmo com o dispositivo executando um algoritmo, a forma como seus recursos são dispostos pode ser alterada, oferecendo a possibilidade de particionar temporalmente um algoritmo. Novas linhas de FPGAs já são fabricadas com opção de reconfiguração dinâmica parcial, i.e., é possível reconfigurar áreas selecionadas de uma FPGA enquanto o restante continua em operação. No entanto, para que esta nova tecnologia se torne largamente difundida é necessário o desenvolvimento de uma metodologia própria, que ofereça soluções eficazes aos novos desdobramentos do projeto digital. Em particular, uma das principais dificuldades apresentadas por esta abordagem refere-se à maneira de particionar o algoritmo, de forma a minimizar o tempo necessário para completar sua tarefa. Este manuscrito oferece uma metodologia de projeto para dispositivos dinamicamente reconfiguráveis, com ênfase no problema do particionamento temporal de circuitos, tendo como aplicação alvo uma família de algoritmos, utilizados principalmente em Bioinformática, representada pelo classificador binário conhecido como Support Vector Machine. Algumas técnicas de particionamento para FPGA Dinamicamente Reconfigurável, especificamente aplicáveis ao particionamento de FSM, foram desenvolvidas para garantir que um projeto dominado por fluxo de controle seja mapeado numa única FPGA, sem alterar sua funcionalidade. / Systems based on general-purpose processors are characterized by a flexibility to design changes, although with a computational performance below those based on optimized dedicated circuits. The implementation of algorithms in reconfigurable devices, known as Field Programmable Gate Arrays, FPGAs, offers a solution with a trade-off between the processor\'s flexibility and the dedicated circuit\'s performance. With FPGAs it is possible to have their hardware resources configured by software, with a smaller granularity than that of the general-purpose processor and greater flexibility than that of dedicated circuits. Current versions of FPGAs present a reconfiguration time sufficiently small as to make feasible dynamic reconfiguration, i.e., even with the device executing an algorithm, the way its resources are displayed can be modified, offering the possibility of temporal partitioning of an algorithm. New lines of FPGAs are already being manufactured with the option of partial dynamic reconfiguration, i.e. it is possible to reconfigure selected areas of an FPGA anytime, while the remainder area continue in operation. However, in order for this new technology to become widely adopted the development of a proper methodology is necessary, which offers efficient solutions to the new stages of the digital project. In particular, one of the main difficulties presented by this approach is related to the way of partitioning the algorithm, in order to minimize the time necessary to complete its task. This manuscript offers a project methodology for dynamically reconfigurable devices, with an emphasis on the problem of the temporal partitioning of circuits, having as a target application a family of algorithms, used mainly in Bioinformatics, represented by the binary classifier known as Support Machine Vector. Some techniques of functional partitioning for Dynamically Reconfigurable FPGA, specifically applicable to partitioning of FSMs, were developed to guarantee that a control flow dominated design be mapped in only one FPGA, without modifying its functionality.

Drawing on multiple theoretical lenses, this research studies continuous transformation, or ‘morphing’, of a business process resource network (BPRN). The aim is to further our understanding of continuous organisational change at the lowest levels of analysis within an organisation: that is, at the resource level, and that resource’s relationships to other resources as they exist within a BPRN. Data was gathered from a single, in depth case study. Analysis was achieved by means of mapping BPRN evolution using ‘temporal bracketing’, ‘visual’ and ‘narrative’ approaches (Langley, 1999). The analysis revealed two mechanisms that appear to govern microstate morphing: bond strength and stakeholder expectation. In addition, four factors emerged as important: environmental turbulence, timing and timeliness of changes, concurrency of changes, and enduring business logic. An emergent model of microstate morphing which acknowledges the importance of socio-materiality in actor network morphogenesis (ANM) is presented. This study shows how effective relationships and configuration of resources within the BPRN can be achieved to facilitate timely, purposeful morphing. Five propositions are offered from the emergent ANM model. Specifically, these relate to the conditional operating parameters and the identified generative mechanisms for continuous organisational transformation within the BPRN. Implications for practice are significant. A heuristic discussion guide containing a series of questions framed around the ANM model to highlight the challenges of microstate morphing for practitioners is proposed. Two routes for future research are suggested: replication studies, and quantifying BPRN change in relation to an organisation’s environment using a ii survey instrument and inferential statistical analysis based on the ANM model features and propositions.

Composição de serviços é um tópico que tem atraído cada vez mais o interesse por parte de pesquisadores na área de sistemas distribuídos. Além disso, o interesse por ambientes baseados em nuvem tem crescido significativamente conforme o seu uso aumenta e se firma como um importante modelo de negócios. Coreografias são formas de composições de serviços em que não há pontos centrais de falha; a responsabilidade da sua execução é distribuída entre os vários serviços componentes. Devido à natureza distribuída do fluxo de informações e dados de controle, o cumprimento de \\textit{Service Level Agreements} (SLAs) depende estritamente do monitoramento da Qualidade de Serviços (QoS), recursos virtuais da nuvem e mecanismos de reconfiguração dinâmica, capazes de automaticamente adaptar composições a mudanças de estado no sistema. Nesta dissertação, abordamos o estudo do gerenciamento de QoS em coreografias de serviços. Para isso desenvolvemos um sistema de middleware capaz de implantar e gerenciar o QoS de composições. Este teve seu desempenho avaliado utilizando o serviço Amazon EC2. Os resultados da avaliação mostram que com pouco esforço por parte dos desenvolvedores de composições, é possível cumprir o SLA de composições dentro do esperado utilizando escalabilidade horizontal ou vertical provida pelo middleware automaticamente. Adicionalmente, a nossa proposta traz economias em relação ao custo de implantação pois diminui a quantidade de recursos subutilizados. / Service composition has been a hot topic that has attracted the interesting of researchers in the distributed system area. Moreover, the interesting in cloud computing based environment has grown significantly. Its use has grown and it became to be a important business model. Choreographies are an specific kind of service composition that has no single point of failure; the responsibility of execution is distributed among the services. Due to the distributed nature of the these systems, the fulfilment of Service Level Agreements (SLAs) depends strictly on and automatic way to monitoring Quality of Service (QoS) and virtual computional resources as well as dinamic reconfiguration mechanisms, to be capable of automatically adapting compositions to changing environment. In this work, we studied QoS management in service choreographies. In order, we devised a middleware system capable of deploy service compositions and manage QoS of them. The middleware was evaluated using the Amazon EC2 cloud provider. The results shows that with less effort from the composition providers, it is possible to fulfil SLAs using horizontal or vertical scalability provided by the middleware automatically. Additionaly, our proposal brings up a cost reduction of deploy by decreasing the amount of underused resources.

Thesis deals with the topic of computational scheduling of production with dynamic reconfigurations and maintenance. The problem is formally defined by a mathematical model named Resource Constrained Project Scheduling Problem which was extended by dynamic reconfiguration and maintenance. Number of different schedule generation algorithms were proposed based on this model. Also methods of solution optimization based on genetic algorithms were described. The typology of production orders of which different task types are created was described in the experimental part. The result of the experiments is clear recommendation of scheduling algorithm for given task type. For the conclusion, thesis deals with the case study of choice of suitable solution for specific production companies.

This master thesis describes design and implementation of a robot controller for autonomous movement in a maze. Robot represents an exemplary system, which is designed for testing and validation of fault-tolerance methodologies. A part of this work contains introduction to reliability of digital systems, especially those which are based on Field Programmable Gate Array (FPGA). Moreover, this introduces techniques that ensure robustness against faults in digital systems; attention is devoted to the usage of FPGA technology in this area and a technique called partial dynamic reconfiguration.

The advances in mobile telecommunication networks as well as in mobile device technology have stimulated the development of a wide range of mobile applications. While it is sensible to install at least some components of applications on mobile devices to gain independence of rather unreliable mobile network connections, it is difficult to decide about the suitable application components and the amount of data to be provided. Because the environment of a mobile device can change and mobile business processes evolve over time, the mobile system should adapt to these changes dynamically to ensure productivity. In this paper, we present a mobile middleware that targets typical problems of mobile applications and dynamically adapts to context changes at runtime by utilizing reconfiguration triggers.

The semiconductor industry has been driven by Moore's law for almost half a century. Miniaturization of device size has allowed more transistors to be packed into a smaller area while the improved transistor performance has resulted in a significant increase in frequency. Increased density of devices and rising frequency led, unfortunately, to a power density problem which became an obstacle to further integration. The processor industry responded to this problem by lowering processor frequency and integrating multiple processor cores on a die, choosing to focus on Thread Level Parallelism (TLP) for performance instead of traditional Instruction Level Parallelism (ILP). While continued scaling of devices have provided unprecedented integration, it has also unfortunately led to a few serious problems: The first problem is that of increasing rates of system failures due to soft errors and aging defects. Soft errors are caused by ionizing radiations that originate from radioactive contaminants or secondary release of charged particles from cosmic neutrons. Ionizing radiations may charge/discharge a storage node causing bit flips which may result in a system failure. In this dissertation, we propose solutions for online detection of such errors in microprocessors. A small and functionally limited core called the Sentry Core (SC) is added to the multicore. It monitors operation of the functional cores in the multicore and whenever deemed necessary, it opportunistically initiates Dual Modular redundancy (DMR) to test the operation of the cores in the multicore. This scheme thus allows detection of potential core failure and comes at a small hardware overhead. In addition to detection of soft errors, this solution is also capable of detecting errors introduced by device aging that results in failure of operation. The solution is further extended to verify cache coherence transactions. A second problem we address in this dissertation relate to power concerns. While the multicore solution addresses the power density problem, overall power dissipation is still limited by packaging and cooling technologies. This limits the number of cores that can be integrated for a given package specification. One way to improve performance within this constraint is to reduce power dissipation of individual cores without sacrificing system performance. There have been prior solutions to achieve this objective that involve Dynamic Voltage and Frequency Scaling (DVFS) and the use of sleep states. DVFS and sleep states take advantage of coarse grain variation in demand for computation. In this dissertation, we propose techniques to maximize performance-per-power of multicores at a fine grained time scale. We propose multiple alternative architectures to attain this goal. One of such architectures we explore is Asymmetric Multicore Processors (AMPs). AMPs have been shown to outperform the symmetric ones in terms of performance and Performance-per-Watt for a fixed resource and power budget. However, effectiveness of these architectures depends on accurate thread-to-core scheduling. To address this problem, we propose online thread scheduling solutions responding to changing computational requirements of the threads. Another solution we consider is for Symmetric Multicore processors (SMPs). Here we target sharing of the large and underutilized resources between pairs of cores. While such architectures have been explored in the past, the evaluations were incomplete. Due to sharing, sometimes the shared resource is a bottleneck resulting in significant performance loss. To mitigate such loss, we propose the Dynamic Voltage and Frequency Boosting (DVFB) of the shared resources. This solution is found to significantly mitigate performance loss in times of contention. We also explore in this dissertation, performance-per-Watt improvement of individual cores in a multicore. This is based on dynamic reconfiguration of individual cores to run them alternately in out-of-order (OOO) and in-order (InO) modes adapting dynamically to workload characteristics. This solution is found to significantly improve power efficiency without compromising overall performance. Thus, in this dissertation we propose solutions for several important problems to facilitate continued scaling of processors. Specifically, we address challenges in the area of reliability of computation and propose low power design solutions to address power constraints.

Cette thèse s'intéresse à la définition de mécanismes, aussi bien au niveau logiciel que matériel, facilitant la gestion des systèmes-sur-puce hétérogènes et dynamiquement reconfigurable (HRSoC). L'hétérogénéité de ses architectures se manifeste par la présence à la fois de processeurs de calcul généralistes et de modules matériels reconfigurables. L'objectif de cette thèse est de permettre à un développeur d'application de s'abstraire de cette hétérogénéité en ce qui concerne l'allocation des tâches sur les différentes unités de calcul disponibles. Cette abstraction passe par une première phase d'homogénéisation des interfaces utilisateurs (API) et la définition d'un modèle de thread matériel, au même titre qu'il existe des threads logiciels. Cette homogénéisation se poursuit ensuite dans la gestion de ces threads matériels. Nous avons implémenté des services au niveau du système d'exploitation permettant de sauvegarder, préempter, et restaurer le contexte d'un thread matériel. Des outils de conception ont également été développés afin de surpasser le problème de la relocation d'un thread matériel au sein d'un FPGA. Enfin, la dernière étape a été d'étendre l'accès aux services offerts par tous les systèmes d'exploitation distribués au sein de la plateforme à tous les threads s'exécutant sur celle-ci, indépendamment de leur localisation. Ceci a été réalisé via une implémentation originale de l'API MRAPI. Avec ces trois étapes, nous avons apporté une base solide afin, dans le futur, de proposer au développeur un flot de conception dédié aux architectures HRSoC lui permettant de procéder à une exploration architecturale précise de son système. Finalement, afin d'éprouver le fonctionnement de ces mécanismes, nous avons réalisé une plateforme de démonstration sur FPGA Virtex 5 mettant en scène une application de suivi de cibles dynamique. / This thesis aims to define software and hardware mechanisms helping in the management the Heterogeneous and dynamically Reconfigurable Systems-on-Chip (HRSoC). The heterogeneity is due to the presence of general processing units and reconfigurable IPs. Our objective is to provide to an application developer an abstracted view of this heterogeneity, regarding the task mapping on the available processing elements. First, we homogenize the user interface defining a hardware thread model. Then, we pursue with the homogenization of the hardware threads management. We implemented OS services permitting to save and restore a hardware thread context. Conception tools have also been developed in order to overcome the relocation issue. The last step consisted in extending the access to the distributed OS services to every thread running on the platform. This access is provided independently from the thread location and is is realized implementing the MRAPI API. With these three steps, we build a solid basis to, in future work, provide to the developer, a conception flow dedicated to HRSoC allowing to perform precise architectural space explorations. Finally, to validate these mechanisms, we realize a demonstration platform on a Virtex 5 FPGA running a dynamic tracking application.

Malgré des avantages certains en terme d'adaptabilité et en gain de surface, la reconfiguration dynamique sur FPGA a du mal à être utilisée dans l'industrie. Le manque de moyens et de méthodes d'évaluation d'une telle architecture en est la cause majeure. Pire, aucun outil officiel ne permet aux développeurs de déterminer facilement un ordonnancement de la reconfiguration adapté pour une architecture donnée. Cette thèse s'inscrit dans ce contexte et propose une méthodologie de modélisation SystemC d'architectures reconfigurables dynamiquement. Cet outil d'aide à la conception permet de faire gagner un temps considérable lors de la phase de conception en fournissant une première estimation des performances et des ressources nécessaires au développement de l'architecture. Il permet également le développement et la validation de scénarios d'ordonnancement de la reconfiguration, tout en respectant les contraintes temps réel liées à l'application. Afin de valider notre modèle sur une application réelle, des IP de transcodage vidéo ont été développées et seront détaillées. Cette application consiste en la réalisation d'un transcodeur H.264/MPEG-2, rendu auto-adaptable grâce à l'utilisation de la reconfiguration dynamique. Ces travaux ont été menés dans le cadre du projet ARDMAHN financé par l'Agence Nationale de la Recherche portant la référence ANR-09-SEGI-001 / Despite clear benefits in terms of fexibility and surface efficiency, dynamic reconfiguration of FPGAs is still finding it hard to break through into massive industrial project. One of the main reasons is the lack of means and methods for evaluation of reconfigurable architectures. Worse, main FPGA vendors do not provide official tools allowing developers to easily determine an optimal scheduling reconfiguration for a specific architecture. Within this framework, the proposed research work described in this thesis proposes a methodology for modeling dynamically reconfigurable architectures based on SystemC. The proposed methodology allows designers to save significant time during the design phases of an application specific reconfigurable architecture by providing an initial estimate of performance and resources needed for its development. It also allows development and validation of scheduling reconfiguration scenarios, while respecting real-time constraints associated with the given application. To validate our methodology on a real application, video transcoding IP have been developed and tested. This application consists in the realization of a H.264/MPEG-2 transcoder made self-adaptable through the use of dynamic reconfiguration. This work was conducted as a part of the ARDMAHN project sponsored by the National Research Agency (Agence Nationale de Recheche) with the reference number ANR-09-SEGI-001

Les travaux présentés dans cette thèse sont effectuées dans le cadre des Systèmes sur puce (SoC, Systemon Chip) et la conception de systèmes embarqués en temps réel, notamment dédiés au domaine de la reconfiguration dynamique, liés à ces systèmes complexes. Dans ce travail, nous présentons un nouveau flot de conception basé sur l'Ingénierie Dirigée par les Modèles (IDM/MDE) et le profilMARTE pour la conception conjointe du SoC, la spécification et la mise en oeuvre de ces systèmes sur puce reconfigurables, afin d'élever les niveaux d'abstraction et de réduire la complexité du système. La première contribution relative à cette thèse est l'identification des parties de systèmes sur puce reconfigurable dynamiquement qui peuvent être modélisées au niveau d'abstraction élevé. Cette thèse adapte une approche dirigée par l'application et cible les modèles d'application de haut niveau pour être traités comme des régions dynamiques des SoCs reconfigurables. Nous proposons aussi des modèles de contrôle générique pour la gestion de ces régions au cours de l'exécution en temps réel. Bien que cette sémantique puisse être introduite à différents niveaux d'abstraction d'un environnent pour la conception conjointe du SoC, nous insistons tout particulièrement sur sa fusion au niveau du déploiement, qui relie la propriété intellectuelle avec les éléments modélisés à haut niveau de conception. En outre, ces concepts ont été intégrés dans le méta-modèleMARTE et le profil correspondant afin de fournir une extension adéquate pour exprimer les caractéristiques de reconfiguration à la modélisation de haut niveau. La seconde contribution est la proposition d'un méta-modèle intermédiaire, qui isole les concepts présents au niveau transfert de registre (RTL-Register Transfer Level). Ce méta-modèle intègre les concepts chargés de l'exécution matérielle des applications modélisées, tout en enrichissant la sémantique de contrôle, provoquant la création d'un accélérateur matériel reconfigurable dynamiquement avec plusieurs implémentations disponibles. Enfin, en utilisant les transformations de modèlesMDE et les principes correspondants, nous sommes en mesure de générer des codeHDL équivalents à différentes implémentations de l'accélérateur reconfigurable ainsi que différents codes source en langage C/C++ liés au contrôleur de reconfiguration, qui est finalement responsable de la commutation entre les différentes mplémentations. Enfin, notre flot de conception a été vérifié avec succès dans une étude de cas liée à un système anti-radar de détection de collision. Une composante clé intégrante de ce système a été modélisée en utilisant les spécifications MARTE étendu et le code généré a été utilisé dans la conception et la mise en oeuvre d'un SoC sur un FPGA reconfigurable dynamiquement.