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The increased power consumption and power density demands of modern technologies combined with the focus on global energy savings have increased the demands on DC/DC power supplies. DC/DC converters are ubiquitous in everyday life, found in products ranging from small handheld electronics requiring a few watts to warehouse sized server farms demanding over 50 megawatts. To improve efficiency and power density while reducing complexity and cost the modular building block approach is gaining popularity. These modular building blocks replace individually designed specialty power supplies, providing instead an optimized complete solution. To meet the demands for lower loss and higher power density, higher efficiency and higher frequency must be targeted in future designs. The objective of this dissertation is to explore and propose methods to improve the power density and performance of point of load modules ranging from 10 to 600W. For non-isolated, low current point of load applications targeting outputs ranging from one to ten ampere, the use of a three level converter is proposed to improve efficiency and power density. The three level converter can reduce the voltage stress across the devices by a factor of two compared to the traditional buck; reducing switching losses, and allowing for the use of improved low voltage lateral and lateral trench devices. The three level can also significantly reduce the size of the inductor, facilitating 3D converter integration with a low profile magnetic by doubling the effective switching frequency and reducing the volt-second across the inductor. This work also proposes solutions for the drive circuit, startup, and flying capacitor balancing issues introduced by moving to the three level topology. The emerging technology of gallium nitride can offer the ability to push the frequency of traditional buck converters to new levels. Silicon based semiconductors are a mature technology and the potential to further push frequency for improved power density is limited. GaN transistors are high electron mobility transistors offering a higher band gap, electron mobility, and electron velocity than Si devices. These material characteristics make the GaN device more suitable for higher frequency and voltage operation. This work will discuss the fundamentals of utilizing the GaN transistor in high frequency buck converter design; addressing the packaging of the GaN transistor, fundamental operating differences between GaN and Si devices, driving of GaN devices, and the impact of dead time on loss in the GaN buck converter. An analytical loss model for the GaN buck converter is also introduced. With significant improvements in device technology and packaging, the circuit layout parasitics begins to limit the switching frequency and performance. This work will explore the design of a high frequency, high density 12V integrated buck converter, identifying the impact of parasitics on converter performance, propose design improvements to reduce critical parasitics, and assess the impact of frequency on passive integration. The final part of this research considers the thermal design of a high density 3D integrated module; this addresses the thermal limitations of standard PCB substrates for high power density designs and proposes the use of a direct bond copper (DBC) substrate to improve thermal performance in the module. For 48V isolated applications, the current solutions are limited in frequency by high loss generated from the use of traditional topologies, devices, packaging, and transformer design. This dissertation considers the high frequency design of a highly efficient unregulated bus converter targeting intermediate bus architectures for use in telecom, networking, and high end computing applications. This work will explore the impact of switching frequency on transformer core volume, leakage inductance, and winding resistance. The use of distributed matrix transformers to reduce leakage inductance and winding resistance, improving high frequency transformer performance will be considered. A novel integrated matrix transformer structure is proposed to reduce core loss and core volume while maintaining low leakage inductance and winding resistance. Lastly, this work will push for higher frequency, higher efficiency, and higher power density with the use of low loss GaN devices. / Ph. D.

With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data centers have replaced the 12V DC server rack distribution with a 48V DC distribution, producing a significant overall system efficiency improvement. However, 48V rack architecture raises significant challenges for the voltage regulator modules (VRMs) required for powering the processor. The 48V VRM in the vicinity of the CPU needs to be designed with very high efficiency, high power density, high light-load efficiency, as well as meet all transient requirements by the CPU and GPU. Transferring the well-developed multi-phase buck converter used in the 12V VRM to the 48V distribution platform is not that simple. The buck converter operating with 48V, stepping down to sub 2V, will be subjected to significant switching related loss, resulting in lower overall system efficiency. These challenges drive the need to look for more efficient architectures for 48V VRM solutions. Two-stage conversions can help solve the design challenges for 48V VRMs. A first-stage unregulated converter is used to step-down the 48V to a specific intermediate bus voltage. This voltage will feed a multi-phase buck converter that powers the CPU. An unregulated LLC converter is used for the first-stage converter, with zero voltage switching (ZVS) operation for the primary side switches, and zero current switching (ZCS) along with ZVS operation, for the secondary side synchronous rectifiers (SRs). The LLC converter can operate at high frequency, in order to reduce the magnetic components size, while achieving high-efficiency. The high-efficiency first-stage, along with the scalability and high bandwidth control of the second-stage, allows this architecture to achieve high-efficiency and power density. This architecture is simpler to adopt by industry, by plugging the unregulated converter before the existing multi-phase buck converters on today's platforms. The first challenge for this architecture is the transformer design of the first-stage LLC converter. It must avoid all of the loss associated with high frequency operations, and still achieve high power density without scarifying efficiency. In this thesis, the integrated matrix transformer structure is optimized by SR integration with windings, interleaved primary side termination, and a better PCB winding arrangement to achieve high-efficiency and power density, and minimize the losses associated with high-frequency operations. The second challenge is the light load efficiency improvement. In this thesis a light load efficiency improvement is proposed by a dynamic change of the intermediate bus voltage, resulting in more than 8 % light load efficiency improvements. The third challenge is the selection of the optimal bus voltage for the two-stage architecture. The impact of different bus voltages was analyzed in order to maximize the overall conversion efficiency. Multiple 48V unregulated converters were designed with maximum efficiency >98 %, and power densities >1000 W/in3, with different output voltages, to select the optimal bus voltage for the two-stage VRM. Although the two-stage VRM is more scalable and simpler to design and adopt by current industry, the efficiency will reduce as full power flows in two cascaded DC/DC converters. Single-stage conversion can achieve higher-efficiency and power-density. In this thesis, a quasi-parallel Sigma converter is proposed for the 48V VRM application. In this structure, the power is shared between two converters, resulting in higher conversion efficiency. With the aid of an optimized integrated magnetic design, a Sigma converter suitable for narrow voltage range applications was designed with 420 W/in3 and a maximum efficiency of 94 %. Later, another Sigma converter suitable for wide voltage range applications was designed with 700W/in3 and a maximum efficiency of 95 %. Both designs can achieve higher efficiency than the two-stage VRM and all other state-of-art solutions. The challenges associated with the Sigma converter, such as startup and closed loop control were addressed, in order to make it a viable solution for the VRM application. The 48V rack architecture requires regulated 12V output converters for various loads. In this thesis, a regulated LLC is used to design a high-efficiency and power-density 48V bus converter. A novel integration method of the inductor and transformer helps the LLC achieve the required regulation capability with minimum losses, resulting in a converter that can provide 1KW of continuous power with efficiency of 97.8 % and 700 W/in3 power density. This dissertation discusses new power architectures with an optimized design for the 48V rack architectures. With the academic contributions in this dissertation, different conversion architectures can be utilized for 48V VRM solutions that solve all of the challenges associated with it, such as scalability, high-efficiency, high density, and high BW control. / Doctor of Philosophy / With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. The data center manufacturers have recently adopted a more efficient architecture that supplies a 48V DC server rack distribution instead of a 12V DC distribution to the server motherboard. This helped reduce costs and losses, but as a consequence, raised a challenge in the design of the DC/DC voltage regulator modules (VRM) supplied by the 48V, in order to power the CPU and GPU. In this work, different architectures will be explored for the 48V VRM, and the trade-off between them will be evaluated. The main target is to design the VRM with very high-efficiency and high-power density to reduce the cost and size of the CPU/GPU motherboards. First, a two-stage power conversion structure will be used. The benefit of this structure is that it relies on existing technology using the 12V VRM for powering the CPU. The only modification required is the addition of another converter to step the 48V to the 12V level. This architecture can be easily adopted by industry, with only small modifications required on the system design level. Secondly, a single-stage power conversion structure is proposed that achieves higher efficiency and power density compared to the two-stage approach; however, the structure is very challenging to design and to meet all requirements by the CPU/GPU applications. All of these challenges will be addressed and solved in this work. The proposed architectures will be designed using an optimized magnetic structure. These structures achieve very high efficiency and power density in their designed architectures, compared to state-of-art solutions. In addition, they can be easily manufactured using automated manufacturing processes.

As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors. / Doctor of Philosophy / Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

The trend in isolated DC/DC bus converters is to increase the output power in the same brick form factors that have been used in the past. Traditional intermediate bus converters (IBCs) use silicon power metal oxide semiconductor field effect transistors (MOSFETs), which recently have reached the limit in terms of turn on resistance (RDSON) and switching frequency. In order to make the IBCs smaller, the switching frequency needs to be pushed higher, which will in turn shrink the magnetics, lowering the converter size, but increase the switching related losses, lowering the overall efficiency of the converter. Wide-bandgap semiconductor devices are becoming more popular in commercial products and gallium nitride (GaN) devices are able to push the switching frequency higher without sacrificing efficiency. GaN devices can shrink the size of the converter and provide better efficiency than its silicon counterpart provides. A survey of current IBCs was conducted in order to find a design point for efficiency and power density. A two-stage converter topology was explored, with a multiphase buck converter as the front end, followed by an LLC resonant converter. The multiphase buck converter provides regulation, while the LLC provides isolation. With the buck converter providing regulation, the switching frequency of the entire converter will be constant. A constant switching frequency allows for better electromagnetic interference (EMI) mitigation. This work includes the details to design and implement a hard-switched multiphase buck converter with planar magnetics using GaN devices. The efficiency includes both the buck efficiency and the overall efficiency of the two-stage converter including the LLC. The buck converter operates with 40V - 60V input, nominally 48V, and outputs 36V at 1 kW, which is the input to the LLC regulating 36V – 12V. Both open and closed loop was measured for the buck and the full converter. EMI performance was not measured or addressed in this work. / Master of Science / Traditional silicon devices are widely used in all power electronics applications today, however they have reached their limit in terms of size and performance. With the introduction of gallium nitride (GaN) field effect transistors (FETs), the limits of silicon can now be passed with GaN providing better performance. GaN devices can be switched at higher switching frequencies than silicon, which allows for the magnetics of power converters to be smaller. GaN devices can also achieve higher efficiency than silicon, so increasing the switching frequency will not hurt the overall efficiency of the power converter. GaN devices can handle higher switching frequencies and larger currents while maintaining the same or better efficiencies over their silicon counterparts. This work illustrates the design and implementation of GaN devices into a multiphase buck converter. This converter is the front end of a two-stage converter, where the buck will provide regulation and the second stage will provide isolation. With the use of higher switching frequencies, the magnetics can be decreased in size, meaning planar magnetics can be used in the power converter. Planar magnetics can be placed directly inside of the printing circuit board (PCB), which allows for higher power densities and easy manufacturing of the magnetics and overall converter. Finally, the open and closed loop were verified and compared to the current converters that are on the market in the 48V – 12V area of intermediate bus converters (IBCs).

Modern data center power architecture developing trend is analyzed, efficiency improvement method is also discussed. Literature survey of high frequency isolated power conversion system which is also called solid state transformer is given including application, topology, device and magnetic transformer. Then developing trend of this research area is clearly shown following by research target. State of art wide band gap device including silicon carbide (SiC) and gallium nitride (GaN) devices are characterized and compared, final selection is made based on comparison result. Mostly used high frequency high power DC/DC converter topology dual active bridge (DAB) is introduced and compared with novel CLLC resonant converter in terms of switching loss and conduction loss point of view. CLLC holds ZVS capability over all load range and smaller turn off current value. This is beneficial for high frequency operation and taken as our candidate. Device loss breakdown of CLLC converter is also given in the end. Medium voltage high frequency transformer is the key element in terms of insulation safety, power density and efficiency. Firstly, two mostly used transformer structures are compared. Then transformer insulation requirement is referred for 4160 V application according to IEEE standard. Solid insulation material are also compared and selected. Material thickness and insulation distance are also determined. Insulation capability is preliminary verified in FEA electric field simulation. Thirdly two transformer magnetic loss model are introduced including core loss model and litz wire winding loss model. Transformer turn number is determined based on core loss and winding loss trade-off. Different core loss density and working frequency impact is carefully analyzed. Different materials show their best performance among different frequency range. Transformer prototype is developed following designed parameter. We test the developed 15 kW 500 kHz transformer under 4160 V dry type transformer IEEE Std. C57.12.01 standard, including basic lightning test, applied voltage test, partial discharge test. 500 kHz 15 kW CLLC converter gate drive is our design challenge in terms of symmetry propagation delay, cross talk phenomenon elimination and shoot through protection. Gate drive IC is carefully selected to achieve symmetrical propagation delay and high common mode dv/dt immunity. Zero turn off resistor is achieved with minimized gate loop inductance to prevent cross talk phenomenon. Desaturation protection is also employed to provide shoot through protection. Finally 15 kW 500 kHz CLLC resonant converter is developed based on 4160V 500 kHz transformer and tested up to full power level with 98% peak efficiency. / Master of Science

Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC MOSFETs can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and a Si metal-oxide-semiconductor field-effect-transistor (MOSFET), is still lacking. This work fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by an avalanche in the Si MOSFET. In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4~1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8~2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency-dependent. At 100 kHz, the failure boundary (~1.3 kV) was even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices showed significant but recoverable parametric shifts. Physics-based device simulation and modeling were then performed to understand the circuit test results. The electron trapping in the buffer layer of the GaN HEMT can explain all the above failure and degradation behaviors in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si MOSFET avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs. / M.S. / Power conversion technologies are now inseparable in industrial and commercial applications with widespread solar panels, laptops, data centers, and electric vehicles. Power devices are the critical components of power conversion systems. Since the introduction of Si power metal-oxide-semiconductor field-effect-transistor (MOSFET) in the mid-1970s, it has become the go-to device that enables efficient and reliable power conversion. After decades of practice on Si MOSFET, the device performance has reached the theoretical limit of the Si material. The recent introduction of wide-bandgap (WBG) power transistors, represented by silicon carbide (SiC) and gallium nitride (GaN) devices with superior figures of merits, opens the door for faster and more efficient power systems. To exploit the benefits of WBG devices, researchers need to evaluate the reliability and robustness of these devices comprehensively. The work presented here provides a study on the robustness of one mainstream GaN power transistor – the cascode GaN high-electron-mobility transistor (HEMT). This robustness test replicates the surge events in power electronics systems and exams their impact on power devices. Over the years, people have thoroughly investigated the surge-energy robustness of Si MOSFETs and concluded that Si MOSFETs are very robust against these surge events thanks to the avalanche mechanism. However, GaN HEMTs lack p-n junction structures between the two major electrodes, leading to the lack of avalanche ability. Instead, GaN HEMTs rely on the overvoltage capability to sustain the surge energy. For the first time, this work evaluates the surge-energy and overvoltage ruggedness of cascode GaN HEMTs, a major player in the GaN power device market. By analyzing the device failure mechanism and degradation behaviors, this research work provides insight into the weakness of these devices for both device designers and application engineers.

Wide-bandgap gallium nitride (GaN) high electron mobility transistors (HEMTs) are gaining increased adoption in applications like mobile electronics and data centers. Benefitting from the high channel mobility and the high breakdown field of GaN, GaN power HEMTs enable low specific on-resistance and small capacitance and thus become attractive for high-frequency applications. In addition, most commercial GaN power HEMTs are fabricated on Si substrates up to 8 inches, allowing for a remarkable cost advantage. However, a by-product of the low-cost GaN-on-Si wafer (and conductive Si substrate) is the high voltage drop and high electric field (E-field) in the GaN buffer layers and transition layers sandwiched between the GaN channel and Si substrate. To boost the vertical blocking capability and minimize the leakage current, the GaN buffer layer is usually doped with carbon or iron, which can introduce complex carrier traps. This can further lead to the dynamic shifts of various parameters in GaN-on-Si HEMTs, which can cause their stability and robustness issues in practical circuit operations. This dissertation work studies the robustness and stability of GaN power HEMTs in dynamic power switching. The structures of most GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness and stability. Simple equipment-level static characterization may not reflect the real device characteristics in circuit-level operation. Based on the relevance between the stress condition and the device's safe operating area (SOA), this dissertation is divided into two parts. In each part, two representative GaN power devices, the standalone GaN HEMT, and the GaN-Si cascode HEMT, are studied. The dissertation's first half discusses the GaN HEMT behavior outside of SOA, with a focus on the robustness of GaN HEMTs in overvoltage power switching. This focus is motivated by the lack of avalanche capability of GaN HEMTs, which is a unique device physics distinct from SiC/Si power transistors. Instead of withstanding the surge energy through avalanching, GaN HEMTs rely on their high breakdown voltage margin to withstand the surge energy, which can trigger new degradation and failure mechanisms. Therefore, investigating the GaN HEMTs' robustness in overvoltage switching is of great interest. The robustness study begins with a standalone depletion-mode (D-mode) MIS (Metal-Insulator-Semiconductor) HEMT in an overvoltage hard-switching. The device is found to show a decreased threshold voltage and increased saturation current after stress. These parametric shifts increase as switching cycles increase but reach a saturation point before one million cycles. The root cause is believed to be the impact-ionization-generated holes trapped underneath the insulated gate. This is verified by the physics-based TCAD (Technology Computer-Aided Design) simulation. After the stress, MIS-HEMT cannot fully recover naturally. Applying at positive gate-to-source bias (VGS) is found to be able to accelerate the threshold voltage recovery but not the saturation current recovery, while a 50-V substrate bias is shown to fully recover both parameters. These findings provide new insight into the hole trapping/de-trapping dynamics and the benefits of substrate voltage control in GaN MIS-HEMTs. Then, a cascode GaN HEMT, which contains a D-mode GaN MIS-HEMT and an enhancement-mode (E-mode) Si MOSFET, is studied similarly in overvoltage stress produced by an inductive switching circuit. Parametric shifts are found in cascode GaN HEMTs, including the unstable breakdown voltage and increased on-resistance. The crosstalk between Si MOSFET and GaN HEMT is believed to account for these parametric shifts. A decapsulated device is developed based on the commercial part to monitor the Si MOSFET behavior. Si MOSFET is found to avalanche during the overvoltage switching. The parametric shifts are believed to be due to the avalanche-generated electrons, which are injected into the GaN HEMTs and trapped in the GaN buffer layer. These electron traps alter the E-field distribution of the GaN HEMT and induce parametric shifts. The second half of the dissertation focuses on the GaN HEMT's stability inside the SOA, with a focus on the non-ideal power loss generated in high-frequency switching. The output capacitance (COSS) loss has recently been found to be the dominant loss in soft switching, which is the loss associated with GaN HEMT's COSS when it is charged and discharged. This process should be lossless for an ideal capacitor, but GaN HEMT experiences a hysteresis COSS loss during each charging-discharging cycle due to the COSS instability in dynamic power switching. The COSS loss study starts with an accurate and easy-to-implement test platform, which is proven to have good robustness and repeatability. The measured COSS loss of different types of GaN HEMTs is modeled, followed by the investigation of the COSS loss origin. TCAD simulation reveals the fundamental role of trappings in the cause of COSS loss in standalone GaN HEMTs. For the cascode GaN HEMT, two additional loss mechanisms are involved as compared to the standalone GaN HEMTs: Si avalanche energy loss and GaN early turn-on loss. This makes cascode GaN HEMT experiences much higher COSS loss than standalone GaN HEMTs. The COSS loss of cascode GaN HEMT is quantitively analyzed, and a mitigation strategy is proposed for suppressing the COSS loss of cascode GaN HEMTs. Then, a circuit-level method is proposed to reduce the COSS loss of standalone GaN HEMT by dynamically tuning the substrate bias, which is verified with a standalone D-mode GaN HEMT. The Si substrate bias can follow the drain voltage in a certain ratio by tuning the capacitance ratio between the drain, substrate, and source. It is found that with a substrate bias of 1/4 to 1/2 of the drain voltage, the COSS loss can be reduced by 86%. This result removes a critical roadblock for deploying GaN HEMTs in high-frequency, soft-switching applications. Finally, the COSS loss of similarly rated Si and SiC power transistors is characterized using the developed test platform. The capability of the setup is further broadened to testing power diodes. Some similarities and distinctions are found in the COSS loss behavior between GaN HEMTs and Si/SiC devices. Also, an EDISS validation process is provided for the UIS-based method in an operating class-E converter, verifying the effectiveness and accuracy of the proposed method. This provides important references for selecting the optimal power devices for high-frequency applications. / Doctor of Philosophy / Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are reshaping the power electronics field. They have become increasingly popular in many applications like smartphones, electric vehicles, and data centers. They offer smaller on-resistance and can handle higher voltages compared to traditional silicon-based devices. GaN transistors are built on large-diameter silicon substrates, making them cost-effective but can lead to unique stability and robustness issues. This dissertation investigates the stability and robustness of GaN power HEMTs in high-voltage and high-frequency power switching. Based on the relevance of the studied stress to the device safe-operating-area, the discussion is divided into two parts: The first part looks at how GaN transistors handle situations where they are pushed beyond their safe operating limits, such as during power surges and overvoltage events. These transistors are found to experience changes in their electrical properties after being stressed, which might affect their performance across their lifetime. In addition to unveiling the physics and evolution of such parametric shifts, this work also discovers ways to recover the device parameters and maintain the device functionality. The second part of the research focuses on the stability and non-ideal power loss of GaN transistors within their safe operating area. The high-frequency soft-switching application is being investigated, as it has become a common trend for future power electronics. The study reveals that GaN transistors can produce additional power loss due to the intrinsic electrical instabilities. In addition to unveiling the key impact factors and physics of this loss, this work also develops device designs to suppress this non-ideal power loss significantly, improving the device efficiency in high-frequency applications. Overall, this work provides valuable insights into improving the robustness and efficiency of GaN transistors, which provide guidelines and insights for GaN designers and users to achieve optimal device and system performance.

Pulsed power systems are concerned with the delivery of significant amounts of power in a greatly condensed time frame. To achieve this, energy is often stored in a capacitor, where it can be rapidly discharged. Certain applications require repeated charging and discharging of the load capacitor in a specifically modulated manner; special power electronics systems must be developed for these situations. Existing systems on the market sacrifice a small form factor for greater pulsed power output. The proposed design outlines the development of a compact pulsed power capacitor charger capable of charging a load capacitor to high voltages at a pulse repetition frequency of 30 kHz. Due to the compact form factor, the charger features a unique design of four full-bridge converters modularly connected in Input-Parallel Output-Series configuration. Experimental verification shows that the system exceeds expectations and can be utilized and adapted to fit many pulsed power applications.

With the fast development of information technology (IT) industry, the demand and market volume for off-line power supplies keeps increasing, especially those for desktop, flat-panel TV, telecommunication, computer server and datacenter. An off-line power supply normally consists of electromagnetic interference (EMI) filter, power factor correction (PFC) circuit and isolated DC/DC converter. Isolated DC/DC converter occupies more than half of the volume in an off-line power supply and takes the most control responsibilities, so isolated DC/DC converter is the key aspect to improve the overall performance and reduce the total cost for off-line power supply. On the other hand, of all the power supplies for industrial applications, those for the data center servers are the most performance driven, energy and cost conscious due to the large electricity consumption. The total power consumption of today's data centers is becoming noticeable. Moreover, with the increase in cloud computing and big data, energy use of data centers is expected to continue rapidly increasing in the near future. It is very challenging to design isolated DC/DC converters for datacenters since they are required to provide low-voltage high-current output and fast transient response. The LLC resonant converters have been widely used as the DC-DC converter in off-line power supplies and datacenters due to its high efficiency and hold-up capability. Using LLC converters can minimize switching losses and reduce electromagnetic interference. Almost all the high-end offline power supplies employs LLC converters as the DC/DC converter. But there are three major challenges in LLC converters. Firstly, the control characteristics of the LLC resonant converters are very complex due to the dynamics of the resonant tank. This dissertation proposes to implement a special LLC control method, state-trajectory control, with a low-cost microcontroller (MCU). And further efforts have been made to integrate all the state-trajectory control function into one MCU for high-frequency LLC converters, including start-up and short-circuit protection, fast transient response, light load efficiency improvement and SR driving. Secondly, the transformer in power supplies for IT industry is very bulky and it is very challenging to design. By pushing switching frequency up to MHz with gallium nitride (GaN) devices, the magnetics can be integrated into printed circuit board (PCB) windings. This dissertation proposes a novel matrix transformer structure and its design methodology. On the other hand, shielding technique can be employed to suppress the CM noise for PCB winding transformer. This dissertation proposes a novel shielding technique, which not only suppresses CM noise, but also improves the efficiency. The proposed transformer design and shielding technique is applied to an 800W 400V/12V LLC converter design. Thirdly, the LLC converters have sinusoidal current shape due to the nature of resonance, which has larger root mean square (RMS) of current, as well as larger conduction loss, compared to pulse width modulation (PWM) converter. This dissertation employs three-phase interleaved LLC converters to reduce the circulating energy by inter-connecting the three phases in certain way, and proposed a novel magnetic structure to integrated three inductors and three transformers into one magnetic core. By pushing switching frequency up to 1MHz, all the magnetics can be implemented with 4-layer PCB winding. Additional 2-layer shielding can be integrated to reduce CM noise. The proposed magnetic structure is applied to a 3kW 400V/12V LLC converter. This dissertation solves the challenges in analysis, digital control, magnetic design and EMI in high-frequency DC/DC converters in off-line power supplies. With the academic contribution in this dissertation, GaN devices can be successfully applied to high-frequency DC/DC converters with MHz switching frequency to achieve high efficiency, high power density, simplified but high-performance digital control and automatic manufacturing. The cost will be reduced and the performance will be improved significantly. / Ph. D. / With the fast development of information technology (IT) industry, the demand and market volume for off-line power supplies keeps increasing, especially those for desktop, flat-panel TV, telecommunication, computer server and datacenter. The total power consumption of today’s data centers is becoming noticeable. Moreover, with the increase in cloud computing and big data, energy use of data centers is expected to continue rapidly increasing in the near future. The efficiency of off-line power supplies is very critical for the whole human society in order to reduce the total electricity consumption. And the cost is also a key driving force for the development of novel technology in off-line power supplies due to the large market volume. An off-line power supply normally consists of electromagnetic interference (EMI) filter, power factor correction (PFC) circuit and isolated DC/DC converter. Isolated DC/DC converter occupies more than half of the volume in an off-line power supply and takes the most control responsibilities, so isolated DC/DC converter is the key aspect to improve the overall performance and reduce the total cost for off-line power supply. Among all the DC/DC converter topologies, the LLC resonant converters have been most widely used as the DC/DC converter due to its high efficiency and hold-up capability. But there are three major challenges in LLC converters. Firstly, the control characteristics are very complex due to the dynamics of the resonant tank. To achieve good control performance, very complex and expensive digital controller has to be employed. Secondly, the magnetic components are very bulky, and it is expensive to manufacture them. Thirdly, there is circulating energy in LLC converters due to the nature of resonance, which increases the total loss. To solve these challenges, this dissertation proposes to implement a special control method, state-trajectory control, with a low-cost microcontroller (MCU). All the control functions can be integrated into one simple, low-cost MCU to replace the previous complex and expensive controller. By pushing switching frequency up to MHz with next generation power devices, this dissertation proposes a novel magnetics structure that can be integrated into printed circuit board (PCB) windings to achieve low-cost and automatic manufacturing. Furthermore, this dissertation employs three-phase interleaved LLC converters topology to reduce the circulating energy, and proposed a novel magnetic structure to integrated three inductors and three transformers into one magnetic core with simple 4-layer PCB winding. All the proposed technologies have been verified on hardware prototypes, and significant improvements over industrial state-of-art designs have been demonstrated. To sum up, this dissertation solves the challenges in analysis, digital control, magnetic design and EMI in DC/DC converters for off-line power supplies. With the academic contribution in this dissertation, the cost can be reduced due to the simplified control and automatic manufactured magnetics, and the efficiency can be improved with proper utilization of next generation power devices. This dissertation will improve future DC/DC converter for IT industrial in the three most important aspects of efficiency, power density and cost.