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The assistance of thin film deposition with low-energy ion bombardment influences their final properties significantly. Especially, the application of so-called hyperthermal ions (energy <100 eV) is capable to modify the characteristics of the growing film without generating a large number of irradiation induced defects. The nitrogen ion beam assisted molecular beam epitaxy (ion energy <25 eV) is used to deposit GaN thin films on (0001)-oriented 6H-SiC substrates at 700 C. The films are studied in situ by reflection high energy electron diffraction, ex situ by X-ray diffraction, scanning tunnelling microscopy, and high-resolution transmission electron microscopy. It is demonstrated that the film growth mode can be controlled by varying the ion to atom ratio, where 2D films are characterized by a smooth topography, a high crystalline quality, low biaxial stress, and low defect density. Typical structural defects in the GaN thin films were identified as basal plane stacking faults, low-angle grain boundaries forming between w-GaN and z-GaN and twin boundaries. The misfit strain between the GaN thin films and substrates is relieved by the generation of edge dislocations in the first and second monolayers of GaN thin films and of misfit interfacial dislocations. It can be demonstrated that the low-energy nitrogen ion assisted molecular beam epitaxy is a technique to produce thin GaN films of high crystalline quality.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

Das Wachstum von monolagen dünnen Schichten von InN und GaN/InN auf ZnO wurde untersucht. Ebenso der Einfluss der Verspannung, welche durch das Substrat bedingt ist, auf den Indiumgehalt von (In, Ga)N Heterostrukturen, welche auf GaN und ZnO gewachsen wurden. Alle Proben wurden mittels Molekularstrahlepitaxy gewachsen. Es wurde eine Prozedur entwickelt zum Glühen von ZnO Substraten, um glatte Oberflächen mit Stufenfluss-Morphologie zu erhalten, welche sich für das Wachstum von monolage-dünnen Heterostrukturen eignen. Solche Zn-ZnO und O-ZnO Oberflächen konnten produziert werden, wenn die Proben bei 1050 °C in einer O2 Atmosphäre bei 1 bar für eine Stunde geglüht wurden. Reflection high energy electron diffraction wurde eingesetzt, um in situ den Wachstumsmodus und die Entwicklung des a-Gitterabstandes zu untersuchen. Die kritische Schichtdicke, ab welcher ein Übergang im Wachstumsmodus von glattem zu rauhem Wachstum statt findet, war für das Wachstum von InN auf ZnO geringer als 2 ML und setzt gemeinsam mit dem Beginn der Relaxation ein. Für das Wachstum von GaN auf monolagen-dünnem InN/ZnO konnte gezeigt werden, dass höchstens wenige ML abgeschieden werden können, bevor Relaxation eintritt und/oder eine Vermischung zu (In, Ga)N stattfindet. Untersuchungen durch Röntgenbeugung und Raman Spektroskopie geben Hinweise darauf, dass das Abscheidung der nominalen Struktur 100x(1 ML InN/2 MLs GaN) vermutlich zum Wachstum von (In, Ga)N führte. Die chemische Zusammensetzung war für alle Proben sehr ähnlich mit einem indium Gehält von etwa x: 0.36 und einem Relaxationsgrad von 65% - 73% für Proben, die auf ZnO gewachsen wurde und 95% für Wachstum auf 300 nm In0.19Ga0.81N/GaN. Ein unbeabsichtigter Unterschied im V/III-Verhältnis während des Wachstums von (In, Ga)N Heterostrukturen, auf welchen die Anwesenheit von Metalltröpchen auf manchen Proben hinwies, lies auf einen möglichen Einfluss auf das Relaxationsverhalten und die Oberflächenrauhigkeit schließen. / Several thin InN and GaN/InN films and (In, Ga)N heterostructures were grown using molecular beam epitaxy to investigate their growth mode. InN and GaN/InN films were grown on ZnO substrates and (In, Ga)N heterostructures were grown on (In, Ga)N buffers and ZnO substrates. Fabricating the heterostructures on two different types of substrates was a means of strain engineering to possibly increase the indium content in the (In, Ga)N layers. An annealing procedure was established to treat ZnO substrate to gain smooth, stepped surfaces suitable for ML thin heterostructure devices. Reflection high energy electron diffraction was used to investigate in situ the growth mechanism and evolution of the a-lattice spacing. The critical layer thickness for growth mode transition of InN from smooth to rough is below 2 MLs and fairly coincides with the onset of main relaxation. The deposition of GaN on ML thin InN/ZnO shows that at best a few MLs can be deposited before relaxation and/or intermixing into (In, GaN) takes place. Investigations by X-ray diffraction and Raman spectroscopy indicate that the deposition of a nominal structure of 100x(1 ML InN/2 MLs GaN) seems to result in the growth of (In, Ga)N instead. The average chemical composition was similar for all samples with an indium content close to x: 0.36 and a degree of relaxation between 65%-73% for samples grown on ZnO and 95% for the sample grown on 300 nm In0.19Ga0.81N/GaN pseudo-substrate. The surface was probed with atomic force microscopy and showed that starting with smooth surfaces with root mean square roughness around 0.2 nm there was a considerable roughening during growth and surfaces with grain like morphology and a roughness around 2 to 3 nm was produced. Unintentional differences in V/III ratio during growth of (In, Ga)N heterostructures, indicated by the presence of droplets on some of the sample surfaces, were possible, impacting on the sample relaxation behavior and the surface roughness.

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This work explores how GaN devices and advanced control can improve the power density of battery chargers for the plug-in hybrid electric vehicle. Gallium nitride (GaN) devices are used to increase switching frequency and shrink passive components. An innovative DC link reduction technique is proposed and several practical design issues are solved. A multi-chip-module (MCM) approach is used to integrate multiple GaN transistors into a package that enables fast, reliable, and efficient switching. The on-resistance and output charge are characterized. In a double pulse test, GaN devices show fast switching speed. The loss estimation based on the characterization results shows a good match with the measurement results of a 500 kHz GaN-based boost converter. Topology selection is conducted to identify candidates for the PHEV charger application. Popular topologies are reviewed, including non-isolated and isolated solutions, and single-stage and two-stage solutions. Since the isolated two-stage solution is more promising, the topologies consisting of an AC/DC front-end converter and an isolated DC/DC converters are reviewed. The identified candidate topologies are evaluated quantitatively. Finally, the topology of a full bridge AC/DC plus dual active bridge DC/DC is selected to build the battery charger prototype for fixed switching-frequency, low loss, and low realization complexity. The DC link capacitor is one of the major power density barriers of the charger, as its size cannot be reduced by increasing the switching frequency. This work proposed a charging scheme to reduce the DC link capacitance by balancing the ripple power from input and output given that the double-line-frequency current causes minor impact to the battery pack in terms of capacity and temperature rise. An in-depth analysis of ripple power balance, with converter loss considered, unveils the conditions of eliminating the low-frequency DC link capacitors. PWM-zero-off charging where the battery is charged by a current at double-line-frequency and DC/DC stage is turned off at the zero level of the waveform, is also proposed to achieve a better tradeoff between the DC link capacitor size and the charger efficiency. The practical design issues are outlined and the solutions are given at different levels of implementations, including the full bridge building block, the AC/DC stage, and the DC/DC stage. The full bridge section focuses on the solution of a reliable driving and sensing circuitry design. The AC/DC stage portion stresses the modulator improvement, which solves the often-reported issues of the current spike at the zero-crossing of the line voltage for the high frequency totem-pole bridgeless converter. In the DAB section, analytical expressions are given to model the converter operation at various operating conditions, which match well with the measurement results. The overall charging-system operation including the seamless transition of bi-directional power flow and the charging-profile control is verified on a laboratory GaN charger prototype at 500 kHz and 1.8 kW with an efficiency of 92.4%. To push the power density, some bulky components including the control board, the cooling system, and the chassis are redesigned. Together with other already-verified building blocks including full bridges, magnetics, and capacitors, a high-density mock-up prototype with 125 W/in3 power density is assembled. / Ph. D.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.