In this thesis, various kinds of theory to account for injection locking and pulling in the literature are studied and compared. On this basis, this thesis derives a generalized locking equation when injection signal is modulated signal. In applications, a novel RF sensing circuit for cognitive radio system is proposed using injection locking and frequency demodulation. Detailed circuit architecture and sensing principle are also described in the thesis. In implementation, a hybrid VCO and a CMOS VCO have been separately used with the other components to establish the RF sensing circuit. The simulation relies on a discrete-time numerical method. Comparison between measurement and simulation shows very good agreement. This RF sensing circuit can simultaneously sense frequency and power with a sensing speed up to 400 MHz/ms and a sensing sensitivity as low as -80 dBm, showing that the presented prototype can fast and reliably sense frequency and power for analog and digital modulation signals.

This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduced. It is demonstrated through theory, simulation and measurement results that the half-rate architecture can improve maximum achievable speed by a factor of 1.6. The distribution and alignment of high-frequency clocks across a wide bus of links is a signi¯cant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a bu®er into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional bu®ering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 um digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. Injection locked oscillators (ILOs) are an attractive clocking tool for low-power area- e±cient wireline receivers. In this work, we explored their use as a clock deskew element, a clock recovery unit and a programmable jitter lter. A study of both LC and ring ILOs indicates signi¯cant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting di®erent phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. First, an ILO based half-rate clock recovery technique is presented, which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is veried with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. Second, a clock forwarded 65nm CMOS receiver uses two ILOs to frequency- multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Di®erent data rates and latency mismatch between the clock and data paths are ac- commodated by a jitter tracking bandwidth that is controllable up to 300MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200MHz.

This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduced. It is demonstrated through theory, simulation and measurement results that the half-rate architecture can improve maximum achievable speed by a factor of 1.6. The distribution and alignment of high-frequency clocks across a wide bus of links is a signi¯cant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a bu®er into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional bu®ering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 um digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. Injection locked oscillators (ILOs) are an attractive clocking tool for low-power area- e±cient wireline receivers. In this work, we explored their use as a clock deskew element, a clock recovery unit and a programmable jitter lter. A study of both LC and ring ILOs indicates signi¯cant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting di®erent phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. First, an ILO based half-rate clock recovery technique is presented, which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is veried with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. Second, a clock forwarded 65nm CMOS receiver uses two ILOs to frequency- multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Di®erent data rates and latency mismatch between the clock and data paths are ac- commodated by a jitter tracking bandwidth that is controllable up to 300MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200MHz.

Quadrature LO signal is a key element in many of the RF transceivers which tend to dominate today’s wireless communication technology. The design of a quadrature LC VCO with better phase noise and lower power consumption forms the core of this work. This thesis investigates a coupling mechanism to implement a quadrature voltage controlled oscillator using indirect injection method. The coupling network in this QVCO couples the two LC cores with their super-harmonic and it recycles its bias current back into the LC tank such that the power consumed by the coupling network is insignificant. This recycled current enables the oscillator to achieve higher amplitude of oscillation for the same power consumption compared to conventional design, hence assuring better phase noise. Mathematical analysis has been done to study the mechanism of quadrature operation and mismatch effects of devices on the quadrature phase error of the proposed QVCO. The proposed quadrature LC VCO is designed in TSMC 0.18 μm technology. It is tunable from 2.61 GHz - 2.85 GHz with sensitivity of 240 MHz/V. Its worst case phase noise is -120 dBc/Hz at 1 MHz offset. The total layout area is 1.41 mm^2 and the QVCO core totally draws 3 mA current from 1.8 V supply.

Ο ταλαντωτής αποτελεί σημαντικό κομμάτι κάθε τηλεπικοινωνιακού συστήματος. Το σημαντικότερο στοιχείο της απόδοσής του είναι ο θόρυβος φάσης. Για τη βελτίωσή του χρησιμοποιείται η μέθοδος του injection locking. Με αυτή τη μέθοδο ένα σήμα αναφοράς με καλά χαρακτηριστικά θορύβου χρησιμοποιείται για να βελτιώσει την έξοδο του ταλαντωτή. Χρησιμοποιείται μια τοπολογία τροποποιημένου ταλαντωτή Colpitts, ο οποίος εξομοιώνεται και υλοποιείται. Με τις μετρήσεις που ακολουθούν επιβεβαιώνεται η καλύτερη συμπεριφορά θορύβου που επιτυγχάνει η μέθοδος του injection locking. / Oscillators form an integral part of all communication systems. Their most crucial element regarding performance is phase noise. To improve it we use the method of injection locking. With this method, a reference signal with good noise characteristics is used to improve the output of the oscillator. A modified Colpitts oscillator topology is used which is both simulated and implemented as a circuit board. Measurements confirmed that injection locking improved the characteristics of phase noise.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第22843号 / 工博第4783号 / 新制||工||1748(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 篠原 真毅, 教授 大村 善治, 准教授 後藤 康仁 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

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京都大学 / 新制・課程博士 / 博士(理学) / 甲第23451号 / 理博第4745号 / 新制||理||1680(附属図書館) / 京都大学大学院理学研究科物理学・宇宙物理学専攻 / (主査)教授 田中 耕一郎, 教授 佐々 真一, 教授 金光 義彦 / 学位規則第4条第1項該当 / Doctor of Science / Kyoto University / DFAM

The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases. A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals. A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Oct. 1, 2012 - Oct. 1, 2014

Future wireless communication systems will have higher data transmission rates and energy efficiencies than those used today. This fact raises serious challenges to the design of conventional transceiver architectures. This doctoral research develops energy-efficient RF transmitters and receivers for next-generation wireless communications. It begins with a theoretical analysis of the injection locking of oscillators and a modified Class-E power amplifier (PA) for use in developing the proposed transmitter and receiver. Based on the presented theory, a novel envelope elimination and restoration (EER)/polar transmitter using injection-locked oscillators (ILOs) and a novel cognitive polar receiver using two ILO stages are proposed. The EER/polar transmitter combines the approaches of EER/polar modulation and injection locking to achieve linear amplification with a high gain and high efficiency. Experimental results demonstrate its effectiveness for delivering WCDMA and EDGE signals. Additionally, the cognitive polar receiver utilizes two ILO stages to extract the modulation envelope and phase components of a received nonconstant envelope modulation signal without using a phase-locked loop (PLL)-based carrier recovery circuit. Experiments are conducted to verify the feasibility of the novel architecture by performing £k/4 DQPSK and QPSK demodulation. Rigorous theoretical analysis and experimental verification prove that both the proposed transmitter and the receiver are effective for energy-efficient wireless communications.