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Power estimation of microprocessorsSambamurthy, Sriram 13 December 2010 (has links)
The widespread use of microprocessor chips in high performance applications like
graphics simulators and low power applications like mobile phones, laptops,
medical applications etc. has made power estimation an important step in the
manufacture of VLSI chips. It has become necessary to estimate the power
consumption not only after the circuits have been laid out, but also during the
design of the modules of the microprocessor at higher levels of design
abstraction.
The design of a microprocessor is complex and is performed at multiple layers of
abstraction before it finally gets manufactured. The processor is first
conceptually designed using blocks at the system level, and then modeled using a
high-level language (C, C++, SystemC). This enables the early development of
software applications using these high-level models. The C/C++ model is then
translated to a hardware description language (HDL), that typically corresponds
to the register transfer level (RT-Level). Once the processor is defined at the
RT-Level, it is synthesized into gates and state elements based on user-defined
constraints. In this thesis, novel techniques to estimate the power consumed by
the microprocessor circuits at the gate level and RT-level of abstraction are
presented.
At the gate level, the average power consumed by microprocessor circuits is
straight-forward to estimate, as the implementation is known. However,
estimating the maximum or peak instantaneous power consumed by the
microprocessor as a whole, when it is executing instructions, is a hard problem
due to the high complexity of the state space involved. An hierarchical approach
to estimate the peak power using powerful search techniques and formal tools is
presented in this thesis. This approach has been extended and applied to solve
the problem of estimating the maximum supply drop. Details on this extension and
a discussion of promising results are also presented. In addition, this approach
has been applied to explore the possibility of minimizing the leakage component
of power dissipation, when the processor is idle.
At the register transfer level, estimating the average power consumed by the
circuits of the microprocessor is by itself a challenging problem. This is due
to the fact that their implementation is unknown at this level of abstraction.
The average power consumption directly depends on the implementation. The
implementation, in turn, depends on the performance constraint imposed on the
microprocessor. One of the factors affecting the performance of the
microprocessor, is the speed of operation of its circuits. Considering these
factors and dependencies (for making early design decisions at the RT-Level), a
methodology that estimates the power vs. delay curves of microprocessor circuits
has been developed. This will enable designers to make design decisions for even
rudimentary designs without going through the time consuming process of
synthesis. / text
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Mixed RTL and gate-level power estimation with low power design iteration / Lågeffektsestimering på kombinerad RTL- och grind-nivå med lågeffekts design iterationNilsson, Jesper January 2003 (has links)
<p>In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. </p><p>Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.</p>
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Mixed RTL and gate-level power estimation with low power design iteration / Lågeffektsestimering på kombinerad RTL- och grind-nivå med lågeffekts design iterationNilsson, Jesper January 2003 (has links)
In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing. Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.
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System-level power estimation framework with SystemCHuang, Hong-Jie 29 July 2008 (has links)
Energy consumption will reduce the battery life time and increase the weight and cost of mobile devices. Low-power design methods become an important issue of SOC. Until now, there is no commercial power estimates software in system-level. Users must add power estimation to SystemC simulation environment by themselves. In this paper, we proposed a system-level power estimation framework. Users can use their custom power model, and add power estimation automatically. The proposed framework separates the SystemC simulation environment and power estimation into two independent procedures. First, we generate a data collection SystemC module automatically based on the parameters set up by users. This data collection module will automatically collect the information of parameters from SystemC simulation environment, and send these information to power estimation program. Power estimation program will calculate power consumption according to these parameters and formulas set by user. Users can add power estimation to their SystemC simulation environment quickly and use our framework to analysis the power consumption of their SOC system to find improvement issues. Users can use of our framework to compare and analyze various low-power design methods. In this paper, we applied our framework to estimate the power consumption of a 3D graphics SOC to authenticate the functional and practical ability of our framework.
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System level power estimation for power manageable System-on-chipChou, Hung-I 05 August 2009 (has links)
The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means that it needs more power consumption. Therefore, the essential issue that we are facing now is to reduce the power consumption in order to fit the capacity of the batteries. In the current system level design, there is no presentable commercial tool for designers to estimate the power consumption of the system. This thesis proposes a framework for system level power estimation, which allows the users to add the power models of these modules developed by them in the system level. Moreover, the power models of CPU, memory and bus are also provided. Besides the power models and convenient method to modify these models, a power management unit is also provided. With this unit, the designers can use different power management policies to manage the system¡¦s power consumption and decide its power efficiency. In this thesis, the framework is constructed under the environment of SystemC, so the users can alternate the power model and power management policy rapidly. By using this framework, the designers can more conveniently and rapidly estimate the system¡¦s power consumption and improve the system¡¦s architecture. Therefore, it can fast examine the advantages and disadvantages of various power models and power management policies.
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On the Characterization of Library CellsSulistyo, Jos Budi 01 September 2000 (has links)
In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method. / Master of Science
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ADAPTIVE ONLINE PERFORMANCE AND POWER ESTIMATION FRAMEWORK FOR DYNAMIC RECONFIGURABLE EMBEDDED SYSTEMSMu, Jingqing January 2011 (has links)
Runtime dynamic reconfiguration of field-programmable gate arrays (FPGAs) and devices incorporating microprocessors and FPGA has been successfully utilized to increase performance and reduce power consumption. While previous methods have been successful, they typically do not consider the runtime behavior of the application that can be significantly affected by variations in data inputs, user interactions, and environmental conditions. In this dissertation, we present a dynamically reconfigurable system and design methodology that optimizes performance and power consumption by determining which coprocessors to implement with an FPGA based upon the current application behavior.For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are essential to evaluate the performance and power consumption impact of the hardware coprocessor selection. We present a base profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems.Importantly though, complex interactions between multiple application tasks, non-deterministic execution behavior, and effects of operating system scheduling introduce significant challenges. To address these, we further present an adaptive online performance and power estimation framework suing kernel speedup coefficient adaptation that monitors and adapts the changing application and system behavior for multitasked applications. By exhaustively examining predefined voltage and frequency settings for the microprocessor and hardware kernels, the potential speedup and power reduction can be effectively estimated for each configuration and voltage/frequency settings. These estimates can be utilized to determine the optimal system configuration. At the same time, the kernel speedup coefficients for each kernel can be dynamically updated to account for the difference between the estimated and actual performance measured at runtime.Finally, in order to quickly determine kernel selection and voltage and frequency settlings, we present an efficient, online heuristic performance and power estimation framework that significantly decreases execution time at the cost of a small increase in power consumption. This online heuristic estimation framework achieves significant power reduction compared to software only implementation without performance degradation.
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Une approche système pour l'estimation de la consommation de puissance des plateformes MPSoCKumar Rethinagiri, Santhosh 14 March 2013 (has links) (PDF)
Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dés les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final. Dans cette thèse, nous proposons une méthodologie efficace pour l'estimation de la consommation de puissance des plateformes MPSoC. Cette méthodologie repose sur une combinaison d'une analyse fonctionnelle de la puissance (FLPA) pour l'obtention des modèles de consommation et d'une technique de simulation au niveau transactionnel (TLM) pour calculer la puissance de l'ensemble du système. Fondamentalement, FLPA est proposée pour modéliser le comportement des processeurs en terme de consommation afin d'obtenir des modèles paramétrés de haut niveau. Dans ce travail, FLPA est étendue pour mettre en place des modèles de puissance génériques pour les différentes parties du système (mémoire, logique reconfigurable, etc.). En outre, un environnement de simulation a été développé au niveau transactionnel afin d'évaluer avec précision les activités utilisées dans les modèles de consommation. La combinaison de ces deux parties conduit à une estimation de la puissance hybride qui donne un meilleur compromis entre la précision et la vitesse. La méthodologie proposée a plusieurs avantages: elle estime la consommation du système embarqué dans tous ses éléments et conduit à des estimations précises sans matériel coûteux et complexe. La méthodologie proposée est évolutive pour explorer des architectures complexes embarquées. Notre outil d'estimation de puissance au niveau du système PETS (Power Estimation Tool at System-level) est développé sur la base de la méthodologie proposée. L'efficacité de notre outil PETS en termes de précision et rapidité est validée par des architectures embarquées monoprocesseur et multiprocesseur conçues autour des plateformes OMAP (3530 et 5912) et FPGA Pro Xilinx Virtex II.
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Research on Noise Estimation for LTE systemsChou, Huan-Chin 18 October 2011 (has links)
In this thesis, we study the noise power estimation in the LTE system. Two approaches, the weight method and the subspace method, are considered.
The performance of noise power estimation using the weight method highly depends on the accuracy of the channel estimation.
The channel estimation usually gets poor results under scenarios with long delay spreads. Therefore, the weight method also gets poor result.
To overcome the mentioned drawback, we propose the subspace method which is independent from the channel estimation.
From simulation results, we observe that the subspace method gets bias results. However, the bias depends on the length of the observation window and only gets a little influence from the channel conditions.
Therefore, we can correct the bias using a simple look-up-table approach. Computer simulations show that the subspace method gets the more accurate result than the weight method.
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Estimativa de consumo de energia em nivel de instrução para processadores modelados em ArchC / Instruction level power consumption estimation for ArchC processorsMa, Josue Tzan Hsin 26 October 2007 (has links)
Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-10T16:13:05Z (GMT). No. of bitstreams: 1
Ma_JosueTzanHsin_M.pdf: 3316745 bytes, checksum: c195170ef253c94333ce4727afeae31c (MD5)
Previous issue date: 2007 / Resumo: A constante redução do tamanho e o conseqüente aumento do número de transistores em um mesmo chip faz com que a potência dissipada pelos circuitos digitais aumente exponencialmente. Esse fato, combinado com a crescente demanda por dispositivos portáteis, têm levado à uma crescente preocupação quanto ao consumo de energia. Quanto mais potência é dissipada mais calor é gerado e mais energia é gasta com o seu resfriamento. Como resultado, projetistas estão considerando cada vez mais o impacto de suas decisões nesse quesito. Atualmente, ADLs¹ têm sido utilizadas para projetar novos processadores. Essas linguagens descrevem o comportamento da arquitetura para cada ação ou instrução. ADLs, além de diminuirem o tempo de projeto, são úteis para descobrir problemas arquiteturais em um nível mais elevado. Nesse trabalho, foi desenvolvida uma ferramenta de estimativa de consumo de energia em nível de instrução utilizando-se como base a ADL ArchC e, como estudo de caso, um processador SPARCv8. Como resultado do uso da ferramenta desenvolvida, uma simulação de um programa com estimativa de consumo de energia pode ser realizada 100 vezes mais rápida, na média, em relação ao fluxo tradicional / Abstract: The constant reduction in size and consequential increase in number of transistors inside a chip causes an exponential growth in digital circuit power consumption. Combined with the growing demand for portable electronic devices, this has led to a rising concern about energy consumption. The more power is dissipated, the more heat is generated, and the more energy is spent in the cooling process. As a result, designers have been more and more considering the impact of their decisions on this matter. Currently, ADLs¹ are being used to design new processors. These languages describe the architectural behaviour for each action or instruction. Besides decreasing the time-to-market gap, ADLs are useful in discovering architectural problems at a higher level. This work presents an instruction leveI power estimation tool that uses ArchC ADL as a base, and a SPARCv8 processor as a case study. By using the developed tool, a simulation of a program with estimated power consumption can be accomplished 100 times faster, in average, than the traditional tools / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação
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