As descargas atmosféricas sempre foram tratadas como acontecimentos fortuitos e de força maior, inerentes à vontade do homem. Contudo, mudanças significativas a esse respeito ocorreram recentemente na legislação brasileira, no Código Civil e na norma ABNT NBR 5410: 2004 (Instalações Elétricas de Baixa Tensão). Além disso, em 29 de abril de 2004 foi publicada a Resolução Normativa nº 61 da ANEEL, que estabelece as disposições relativas ao ressarcimento de danos, em equipamentos elétricos instalados em unidades consumidoras, causados por perturbações no sistema elétrico. De acordo com essa nova visão, as descargas atmosféricas devem ser tratadas como fenômenos que podem ter as suas conseqüências previstas, evitadas ou ao menos minimizadas, fazendo com que os custos associados não sejam considerados simplesmente como prejuízos, mas sim passíveis de ressarcimento junto à concessionária. Tais fatores, aliados à inexistência de uma metodologia comum para análise dos prejuízos causados por esse fenômeno, motivaram a realização deste trabalho, que teve por objetivo avaliar os custos decorrentes de descargas atmosféricas em sistemas de distribuição de energia. Além de aspectos técnicos e jurídicos, são discutidos os custos referentes à energia não fornecida, danos em equipamentos, mão-de-obra e ressarcimento de pedidos de indenização por danos (PIDs). Discute-se ainda, embora de forma superficial, a importância de contabilização do custo da imagem da empresa junto aos consumidores. Finalmente, apresenta-se uma metodologia para determinação de tais custos, a qual é aplicada a casos reais, com comparação e análise dos resultados obtidos em diferentes situações. / Lightning discharges have always been treated as Acts of God and force majure events, inherent to man?s will. However, significant changes to this regard have recently occurred in the Brazilian Law, in the Civil Code and on the Brazilian Standard ABNT NBR 5410: 2004 (Low Voltage Electric Installations). In addition, on April 29th, 2004, ANEEL Normative Resolution No. 61 was published, which establishes the provisions regarding reimbursement of damages in electrical equipment installed in consumer units, caused by disturbances in the electrical system. According to this new version, the lightning discharges must be treated as phenomena which may have their consequences foreseen, avoided or at least minimized, causing the associated costs to be considered not only as losses, but also entitled to reimbursement with the operator. Such factors, allied to the non-existence of a common methodology for the review of the losses caused by such phenomenon, motivated the development of this work, which aimed at assessing the lightning-related costs in power distribution systems. In addition to the technical and legal aspects, the costs regarding non-supplied power, equipment damage, labor and indemnity claims (PIDs), are also discussed. Although superficially, the importance of taking into account the cost of the company?s image with the consumers is also discussed. Finally, a methodology for the determination of such costs is presented and applied to actual cases, with comparison and analysis of the results obtained in different situations.

Single stage cycloconverters generally incorporate hard switching at turn on and soft switching at turn off. This hard switching at turn on combined with the slow switching speeds of thyristors (the switch of choice for standard cycloconverters) limits their use to lower frequency applications. This thesis explores the analysis and design of a pulse density modulated (PDM), soft switching cycloconverter. Unlike standard cycloconverters, the controller in this converter does not adjust thyristor firing angles. It lets only complete half cycles of the input waveform through to the output. This allows and requires a much greater frequency step down from the input to the output. The advantages, shortcomings and tradeoffs of this topology are explored as this converter is designed, built and tested. The resulting cycloconverter has many deficiencies, but proves the concept of the PDM soft switching technique. Cases for further improvement and study are outlined. In the end, this converter shows much promise for applications requiring a high step down in frequency, as well as where the lower electromagnetic interference (EMI) of soft switching may be beneficial.

The design, construction and testing of a reverse-osmosis (PV-RO) desalination system for fresh water shortage area is presented. The system operates from salt water or brackish water and can be embedded in a renewable energy power supply system, since many fresh shortage areas are remote and isolated. Special attention is given to the energy efficiency of small-scale reverse osmosis desalination systems. Limitations of conventional control strategy using toggle control are presented. Based on this, an objective of creating a small-scale reverse osmosis desalination system was set out. Initially, the background information is presented. This includes the natural resources crisis and main desalination technologies and the viability of the integration with renewable energy source. A reverse osmosis (RO) desalination system was assembled and set up at the Curtin University of Technology, Perth, Western Australia Supervisor Control And Data Acquisition (SCADA) system was built using a Human Machine Interface software and a programmable logic controller (PLC). Instrumentation that included signal conditioners was made in analysis of the system characteristics. Initial testing of the system was conducted after the system design and configuration was accomplished. Testing results were used as a guideline for the development of the whole system. / Modelling and simulation of the system components in MATLABSimulink is presented, together with a discussion of the control systems modelling and design procedure, in which the aim was to improve the efficiency of the reverse osmosis system. Simulations show the designed reverse osmosis system with Proportional Integral and Derivative (PID) controller has better performance than other controllers. This consequently leads to a lower overall cost of the water, as well as reducing full maintenance cost of the electric drives in the reverse osmosis unit. Additionally, the configuration of the remote control system through General Package Radio System (GPRS) network is depicted. After the PID control algorithm was programmed into the Programmable Logic Controller (PLC), system experiments were carried out in short durations and long durations. System performance was monitored and experimental results prove that the new control strategy applied increase the water productivity and is able to improve the system efficiency up to 35%. Based on the data obtained from the simulations and experiments, Mundoo Island was chosen to be the location for a case study. The electric load profile of the island was derived from the Island Development Committee in Mundoo. / A water demand profile was created and modelled in Matlab to be the input of the reverse osmosis system. The electric load of the reverse osmosis system was generated from Matlab simulation. This result was entered in Hybrid Optimisation Model for Electric Renewables (HOMER) simulator. Having the designed RO unit as one of the electric loads, the entire remote area power supply (RAPS) system was tested in simulations which shows the energy cost is AUS$0.174 per kWh, lower than the Island Development Committee budget estimation of AUS$0.25 per kWh. The cost of the water treatment is very promising at AUS$0.77 per m3.

In this work, single stage power factor corrected AC/DC converters for LEDs / single stage Flyback converter having different configuration from the traditional Flyback and single stage SEPIC converter is investigated. The study involves analysis, circuit design, performance comparisons and implementation. The study covers LEDs / their developments, characteristics and state-of-art in this new technology. The circuits are investigated by means of computer simulations. Operating principles and operating modes are studied along with design calculations. After applying prototypes in laboratory, the simulation results and theoretical analyses are confirmed. The single stage Flyback converter has high voltage input (220-240 Vac), and the output feeds up to 216 HB-LEDs, with the ratings of 24 V, 3.25 A with 90 W. The single stage SEPIC converter with universal input (80-265 Vac) has an output that feeds 21 power LEDs, with 67 V, 0.30 and 20 W ratings.

Denna avhandling presenterar en undersökning av orsakerna och effekterna av timingosäkerhet i Sigma-Delta Analog-Digital-Omvandlare, med speciellt fokus på Sigma-Delta av den switchade kapacitanstypen. Det undersökta området för orsakerna till timingosäkerhet är digital klockgenerering och området för effekterna är sampling. Upplösningsnivån på analysen i detta arbete börjar på beteendenivå och slutar på transistornivå. Samplingskretsen är den intuitiva komponenten att söka i efter orsakerna till effekterna av timing-osäkerhet i en Analog-Digital-Omvandlare eftersom transformationen från reell tid till digital tid sker i samplingskretsen. Därför har prestandaeffekterna av timingosäkerhet i den typiska samplingskretsen för switchad kapacitans Sigma-Delta Analog-Digital-Omvandlare analyserats utförligt, modellerats och beskrivits i denna avhandling. Under analysprocessen har idéer om förbättrade samplingskretsar med naturlig tolerans mot timing-osäkerhet utvecklats och analyserats, och presenteras även. Två typer av förbättrade samplingstopologier presenteras: parallelsamplern och Sigma-Delta-samplern. Den första erhåller tolerans mot timing-osäkerhet genom att utnyttja ett teorem inom statistiken medan den andra är tolerant mot timing-osäkerhet p.g.a. spektral formning som trycker ut brus ur signalens frekvensband. Digital klockgenerering är ett fundamentalt steg i genereringen av multipla klocksignaler som behövs t.ex. i switchade kapacitansversioner av Sigma-Delta Analog-Digital-Omvandlare. Klockgeneratorkretsarna konverterar en tidsreferens, d.v.s. en klocksignal, som vanligen kommer från en faslåst loop till multipla tidsreferenser. De två typerna av klockgenereringskretsar som behandlas i denna avhandling används för att skapa två icke-överlappande klockor från en klocksignal. Processen som undersökts och beskrivits är hur matningsspänningsbrus och substratbrus omvandlas till timing-osäkerhet då en referenssignal passerar genom en av ovannämnda klockgenereringskretsar. Resultaten i denna avhandling har erhållits genom olika analystekniker. Modelleringarna och beskrivningarna har utförts från ett matematiskt och fysikaliskt perspektiv. Detta har fördelen av att kunna förutsäga prestandainfluenser som olika kretsparametrar har utan att behöva utföra datorsimuleringar. Svårigheterna med den matematiska och fysikaliska modelleringen är balansgången mellan olöslighet och överförenkling som måste hittas. Den andra infallsvinkeln är användandet av datorbaserade simuleringsverktyg både för beskrivnings- och verifieringsändamål. Simuleringsverktygen som använts är MATLAB och Spectre/Cadence. Som nämnts har deras syfte varit både som modell- och beskrivningsverifiering och även som ett sätt att erhålla kvantitativa resultat. Generellt talat bryter simuleringsverktyg den mentala kopplingen mellan resultat och diverse kretsparametrar och det kan vara svårt att uppnå en solid prestandaförståelse. Dock är det ibland bättre att erhålla ett prestandamått utan full förståelse än inget mått alls. / This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level. The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band. Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits. The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all. / QC 20100921

Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

Inom Försvarsmakten används motordrivna generatorer för att förse många förbandsenheter med elektricitet. Dagens bullriga och vibrerande elverk är idag möjliga att ersätta med tystare bränsleceller. På köpet erhålls en bättre ergonomi för alla som arbetar i hytter som strömförsörjs av elverk. I rapporten redovisas funktionen för olika typer av bränsleceller, vilka bränslen de använder sig av och hur dessa kan transporteras. Dessutom redovisas hur två elverk används och vilka förbättringar som kan åstadkommas vid byte till bränsleceller. Slutligen analyseras den militära nyttan med ett byte. / In the Armed Forces many units are provided with electricity from generators. It is now possible to replace noisy and vibrating generators used today with more quiet fuel cells. As a bonus, we obtain better ergonomics for those working in units powered by generators. This report describes the function of different types of fuel cells, what fuels they use and how they can be transported. Furthermore it shows how two generators are used and what improvements can be achieved when switching to fuel cells. Finally the military benefit of retrofitting is analyzed.

The Liquid-Salt-Cooled Very High-Temperature Reactor (LS-VHTR) was modeled using the neutronics analysis code SCALE6.0 and the thermal-hydraulics and kinetics modeling code RELAP5-3D with objective to devise, analyze, and evaluate the feasibility and stability of a start-up procedure for this reactor using natural circulation of the coolant and under the Loss Of Offsite Power (LOOP) conditions. This Generation IV reactor design has been studied by research facilities worldwide for almost a decade. While neutronics and thermal-hydraulics analyses have been previously performed to show the performance of the reactor during normal operation and for shutdown scenarios, no study has heretofore been published to examine the active or passive start-up of the reactor. The fuel temperature (Doppler) and coolant density coefficient of reactivity of the LS-VHTR were examined using the CSAS6 module of the SCALE6.0 code. Negative Doppler and coolant density feedback coefficients were calculated. Two initial RELAP5 simulations were run to obtain the steady-state conditions of the model and to predict the changes of the thermal-hydraulic parameters during the shutdown of the reactor. Next, a series of step reactivity additions to the core were simulated to determine how much reactivity can be inserted without jeopardizing safety and the stability of the core. Finally, a start-up procedure was developed, and the restart of the reactor with natural convection of the coolant was simulated. The results of the simulations demonstrated the potential of a passive start-up of the LS-VHTR.

As technology has scaled into nanometer regime, manufacturing variations have emerged as a major limiter of performance (timing) in VLSI circuits. Issues related to timing are addressed in the first part of the dissertation. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under uncertainty such as manufacturing variations. In this dissertation, we propose an efficient sparse-matrix framework for a path-based SSTA. In addition to an efficient framework for doing timing analysis, to improve the accuracy of the timing analysis one needs to address the accuracy of: waveform modeling, and gate delay modeling. We propose a technique based on Singular Value Decomposition (SVD) that accurately models the waveform in a timing analyzer. To improve the gate delay modeling, we propose a closed form expression based on the centroid of power dissipation. This new metric is inspired by our key observation that the Sakurai-Newton (SN) delay metric can be viewed as the centroid of current. In addition to accurately analyzing the timing of a chip, improving timing is another major concern. One way to improve timing is to scale down the threshold voltage (Vth). But scaling down increases the subthreshold leakage current exponentially. Sleep transistors have been proposed to reduce leakage current while maintaining performance. We propose a path-based algorithm to size the sleep transistor to reduce leakage while maintaining the required performance. In the second part of dissertation we address power grid and thermal issues that arise due to the scaling of integrated circuits. In the case of power grid simulation, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The transistor is modeled as a switch in series with an RC and the switch itself is modeled behaviorally. This model allows more accurate prediction of voltage drop compared to the current source model. In the case of thermal simulation, we address the issue of ignoring the nonlinearity of thermal conductivity in silicon. We found that ignoring the nonlinearity of thermal conductivity may lead to a temperature profile that is off by 10° C.

Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text