Les travaux de cette thèse portent sur l’idée de démontrer que la croissance des nanofils entre deux électrodes prédéfinies et plus particulièrement la croissance horizontale à l’intérieur des tranchées d’oxyde peut être utilisée dans l’optique d’une intégration 3D. Cela permettrait donc à terme de pouvoir directement fabriquer les couches actives semi-conductrices d’un transistor MOS dans les niveaux supérieurs d’une puce CMOS tout en respectant le budget thermique, et sans avoir recours à des étapes de collage de puces. Au cours de ce projet de recherche, nous nous sommes intéressés en premier lieu au développement et à l’optimisation du procédé « nanodamascène » mis en place pour guider des nanofils SiGe dans des tranchées d’oxyde directement sur un substrat SiO2/Si. À part de cette technique d’intégration, nous avons aussi utilisé la technique de diélectrophorèse pour orienter et localiser des nanofils dispersés dans une solution liquide entre des électrodes prédéfinies. Les résultats de ces études ont permis en premier lieu de fabriquer des transistors à canaux nanofils sur l’oxyde, avec un objectif final de montrer la possibilité d’établir un transistor dans le BEOL d’une puce CMOS. / The work of this thesis deals with the idea of demonstrating that the growth of nanowires between two predefined electrodes and more particularly the horizontal growth inside the oxide trenches can be used in the context of a 3D integration. This would help to directly manufacture the active semiconductor layers of a MOS transistor in the upper levels of a CMOS chip while respecting the thermal budget, and without resorting to chip bonding steps. During this project, we focused on the development and optimization of the "nanodamascene" process implemented to guide SiGe nanowires in oxide trenches directly on SiO2/Si substrate. Apart from this integration technique, we have also used the dielectrophoresis technique to orient and localize nanowires dispersed in a liquid solution between predefined electrodes. The results of these studies made it possible in the first place to manufacture nanowire channel transistors on the oxide, with a goal of which will be to demonstrate the possibility of establishing a transistor in the BEOL of a CMOS chip.

Les contraintes font maintenant partie des “ boosters ” de la microélectronique au même titre que le SOI (silicium sur isolant) ou le couple grille métallique / diélectrique haute permittivité. Appliquer une contrainte au niveau du canal des transistors MOSFETs (transistors à effet de champ à structure métal-oxyde-semiconducteur) permet d'augmenter de façon significative la mobilité des porteurs de charge. Il y a par conséquent un besoin de caractériser les déformations induites par ces contraintes à l'échelle nanométrique. L'holographie électronique en champ sombre est une technique de MET (Microscopie Électronique en Transmission) inventée en 2008 qui permet d'effectuer des cartographies quantitatives de déformation avec une résolution spatiale nanométrique et un champ de vue micrométrique. Dans cette thèse, la technique a été développée sur le microscope Titan du CEA. Différentes expériences ont été réalisées afin d'optimiser la préparation d'échantillon, les conditions d'illumination, d'acquisition et de reconstruction des hologrammes. La sensibilité et la justesse de mesure de la technique ont été évaluées en caractérisant des couches minces épitaxiées de Si_{1-x}Ge_{x}/Si et en effectuant des comparaisons avec des simulations mécaniques par éléments finis. Par la suite, la technique a été appliquée à la caractérisation de réseaux recuits de SiGe(C)/Si utilisés dans la conception de nouveaux transistors multi-canaux ou multi-fils. L'influence des phénomènes de relaxation, tels que l'interdiffusion du Ge et la formation des clusters de β-SiC a été étudiée. Enfin, l'holographie en champ sombre a été appliquée sur des transistors pMOS placés en déformation uniaxiale par des films stresseurs de SiN et des sources/drains de SiGe. Les mesures ont notamment permis de vérifier l'additivité des deux procédés de déformation. / Strain engineering is now considered as one of the most important boosters of microelectronics among other technologies such as SOI (Silicon On Insulator) and high-κ metal gates. By applying a stress in the channel of MOSFET (Metal Oxyde Semiconductor Field Effect Transistor) devices, the charge carriers mobility can be significantly increased. Consequently, there is now a need for a strain metrology at the nanometer scale. Dark-field electron holography is a TEM (Transmission Electron Microscopy) technique invented in 2008 that allows to map strain with micrometer field-of-view and nanometer spatial resolution. In this thesis, the technique was developed on the CEA Titan microscope. First, different developements were carried out concerning the sample preparation, the illumination/acquisition conditions and the reconstruction of the holograms. The sensitivity and the accuracy of the technique were evaluated through the characterization of Si_{1-x}Ge_{x} layers epitaxied on Si and by comparing the results with mechanical finite element simulations. Then, the technique was applied to the study of annealed SiGe(C)/Si superlattices that are used in the construction of new 3D architectures such as multichannel or multiwires transistors. The influence of the different relaxation mechanisms on the strain especially Ge interdiffusion and β-SiC clusters formation was investigated. Finally, dark-field electron holography was applied to the characterization of uniaxially strained pMOS transistors by SiN liners and recessed SiGe sources and drains. The measurements allowed to confirm the strain additivity of the two processes.

M.Ing. (Electrical and Electronic Engineering) / The possibilities and technology of converters with an alternating voltage link are investigated for high specific power conversion at high frequencies. With a view to the functional description of these power converters, s i muLat i on techniques are considered for both system and circuit analysis. A thorough investigation is made into the design of high frequency power transformers, which play an important role in this class of power circuits. This includes a theoretical analysis in conjunction with the 'practical implementation of a design procedure for minimal eddy current losses in the windings as well as experimental work on losses in ferrite cores. For the remainder of the study, attention is focussed on the two pulse inverter which is responsible for the generation of the alternating voltage in the high frequency link. The suitability of bipolar and field effect transistors for power switching, is critically examined and a voltage compensation on the bipolar Darlington, which reduces on-state losses, yielded good results upon application. A study on the feasibility of non-dissipative snubber techniques on the centre tapped inverter is presented, thus supplying a practical way of reducing switching losses without affecting the efficiency of the system. An additional, yet simple, network is added to the snubber circuits of the two pulse inverter which is operational during low load conditions.' in order also to have low switching losses under these circumstances. Finally a 50 k~v, 10 kHz centre tapped inverter was developed and built.

Un système autonome est composé d’une interface capteur, d’un contrôleur numérique, d’une interface de communication et d’une source d’énergie et sa consommation doit être inférieure à environ 100 microW. Pour réduire la consommation de puissance, des nouveaux composants, les Green Transistor ont fait leur apparition sous différentes topologies, modes de fonctionnement et matériaux alternatifs au silicium. L’interface de communication est composée d’un transistor possédant de grandes performances électriques sous faible alimentation. Les topologies retenues sont le transistor à haute mobilité électronique (HEMT) et le transistor à effet de champ métal/oxyde/semi-conducteur (MOSFET) et seuls les matériaux de la filière III-V à faible énergie de bande interdite, faible masse effective et grande mobilité électronique devraient permettre d’atteindre ces objectifs. Des technologies de HEMTs antimoniés AlSb/InAs ainsi que des MOSFETs InGaAs ont été développées. Les mesures de transistors HEMTs AlSb/InAs ont montré des performances au dessus de 100GHz à 10mW/mm à température ambiante et cryogénique et nous pouvons espérer des transistors où 1mW/mm à 10GHz. Or, les courants de grille importants et la conservation d’un rapport d’aspect élevé dans une structure HEMT limitent la réduction du facteur de mérite puissance-fréquence. Ainsi, la technologie de transistors de type MOS InGaAs a été caractérisée durant ces travaux et les résultats dynamiques sont prometteurs (fT =120GHz, Lg=200nm) même si le processus de fabrication n’est pas complètement optimisé. Une perspective de ce travail est l’utilisation de matériaux antimoines pour la réalisation de MOSFET ultra faible consommation. / An autonomous system is composed of a sensor, a digital controller, a communication interface and an energy source. Its consumption should be less than about 100 microW. To reduce power consumption, new components called the Green transistors have appeared in various topologies, operating modes and alternative materials to silicon. The communication interface consists of a transistor with high performances at low power supply. The topologies used are the high electron mobility transistor (HEMT) and the metal-oxide-semiconductor field-effect transistor (MOSFET) and only III-V-based channels with low bandgap energy, low effective mass and high electron mobility should achieve these goals. Antimonide based HEMTs (AlSb/InAs) and InGaAs MOSFETs technologies have been developed. Measurements of transistors AlSb /InAs HEMTs showed performance above 100GHz at 10mW/mm at room and cryogenic temperatures and transistors which 1mW/mm equals to 10GHz can be expected. However, significant gate currents and a high aspect ratio in a HEMT structure limit the reduction the factor of merit between the power and the cut-off frequency. Thus, the technology of InGaAs MOSFET has been characterized during this work and the RF results are promising (fT = 120GHz, Lg = 200nm) even if the process fabrication is not fully optimized. A perspective of this work is the use of antimonide materials for the realization of ultra low power MOSFET.

Les transistors HEMTs (High Electron Mobility Transistors) de la filière GaN sont destinés à des applications dans les domaines militaire et spatial. C’est pourquoi nous avons étudié l’influence de trois types de stress électriques : à canal ouvert, à canal pincé et NGB (Negative Gate Bias), ainsi que l’influence de neutrons thermalisés avec une fluence pouvant aller jusqu’à 1,7.1012 neutrons.cm-2, sur leurs performances électriques dc.Dans un premier temps, nous avons étudié des HEMTs AlInN/GaN de laboratoire. Pour les trois stress, nous avons observé une dégradation due à la création de pièges accepteurs et donneurs au cours des différents stress et à la présence de pièges préexistants. Nous avons ensuite irradié ces composants par des neutrons thermalisés et avons observé une légère dégradation des performances électriques des transistors non stressés et stressés à canal ouvert ou pincé. En revanche, nous avons mis en lumière une légère amélioration pour les transistors ayant subi un stress NGB. Nous avons également irradié des MOS-HEMTs AlInN/GaN et conclu que ceux-ci étaient plus sensibles vis à vis des irradiations.Dans un deuxième temps, nous avons stressé de manière analogue des HEMTs AlGaN/GaN du commerce. Dans le cas du stress à canal ouvert, nous avons observé une diminution importante du courant de drain tandis que pour les stress à canal pincé et NGB le courant de drain augmente légèrement à cause d’une libération de pièges préexistants sous l’action du champ électrique vertical. Lors des irradiations avec des neutrons thermalisés, ces transistors, stressés ou non, subissent là encore des dégradations. / The GaN based HEMTs (High Electron Mobility Transistors) are excellent candidates for military and spatial applications. That’s why we have analysed the influence of three different types of bias stress: on-state stress, off-state stress and NGB (Negative Gate Bias), and the influence of thermalized neutrons with a fluence up to 1.7x1012 neutrons.cm-2, on their dc electrical performances.First, we have studied laboratory AlInN/GaN HEMTs. For the three conditions of stress, we have observed a degradation due to pre-existing traps and to the creation of acceptor and donor traps during the stress. Then, we have irradiated these components with thermalized neutrons and we have found a small degradation of the electrical performances of unstressed and on-state stressed and off-state stressed transistors. On the other hand, we have highlighted a slight improvement for NGB stressed components. We have also irradiated AlInN/GaN MOS-HEMTs and we have concluded that they are more sensible to irradiation.In a second time we have stressed in the same way commercial AlGaN/GaN HEMTs. For the on-state stress, we have observed an important increase in the drain current. However, the drain current increases for the on-state and NGB stressed components due to a release of electrons from pre-existing traps under vertical electrical field. During the irradiation with thermalized neutrons, the unstressed and stressed transistors are degraded and a small decrease in the drain current is visible.

En dépit d'une amélioration remarquable de la performance des composants électroniques organiques, il y a encore un manque de compréhension théorique rigoureux sur le fonctionnement du composant. Cette thèse est consacrée à la création de modèles pratiques pour composants électroniques organiques à base physique complet, à savoir un modèle compact à base physique. Un modèle compact à base physique d'un élément de circuit est une équation mathématique qui décrit le fonctionnement du composant, et est généralement évaluée par trois critères: si elle est suffisamment simple pour être incorporé dans des simulateurs de circuits, précise pour rendre le résultat des simulateurs utile les concepteurs de circuits et rigoureux pour capturer des phénomènes physiques se produisant dans le composant. Dans ce contexte, les caractéristiques distinctives de l'injection de porteurs de charge et de transport dans les semi-conducteurs organiques sont incorporés dans les modèles avec un effort particulier pour maintenir la simplicité mathématique. L'effet concomitant sur les caractéristiques courant-tension des diodes et des transistors organiques prototypiques sont étudiés. Les méthodes d'extraction des paramètres cohérents aux modèles sont présentés qui permettent la détermination univoque des paramètres de le composant utilisé pour le fonctionnement du composant de modélisation et l'évaluation des performances de le composant et les propriétés des couches minces et des interfaces organiques. Les approches englobent le developement analytique des équations physiques, la simulation numérique à deux dimensions basé sur la méthode des éléments finis et la validation expérimentale. Les modèles compacts originaux et entièrement analytiques et des méthodes d'extraction de paramètres fournissent une compréhension fondamentale sur la façon dont le désordre énergétique dans une couche mince de semi-conducteur organique, décrit par la densité d’etats Gaussienne, affecte les caractéristiques courant-tension observables des composants.Mots-clés : Electronique organique, physique des composants électroniques, modélisation analytique, diodes, transistors à effet de champ, densité d’etats Gaussienne / In spite of a remarkable improvement in the performance of organic electronic devices, there is still a lack of rigorous theoretical understanding on the device operation. This thesis is dedicated to establishing practical models of organic electronic devices with a full physical basis, namely a physically-based compact model. A physically-based compact model of a circuit element is a mathematical equation that describes the device operation, and is generally assessed by three criteria: whether it is sufficiently simple to be incorporated in circuit simulators, accurate to make the outcome of the simulators useful to circuit designers, and rigorous to capture physical phenomena occuring in the device. In this context, distinctive features of charge carrier injection and transport in organic semiconductors are incorporated in the models with a particular effort to maintain mathematical simplicity. The concomitant effect on the current-voltage characteristics of prototypical organic diodes and transistors are studied. Parameter extraction methods consistent to the models are presented which enable unambiguity determination of device parameters used for modeling device operation and assessing device performance and properties of organic thin-films and interfaces. The approaches encompass analytical developement of physical equations, two-dimensional numerical simulation based on finite-element method and experimental validation. The original and fully analytical compact models and parameter extraction methods provide fundamental understanding on how energetic disorder in an organic semiconductor thin-film, described by the Gaussian density of states, affects the observable current-voltage characteristics of the devices.Keywords : Organic electronics, device physics, analytical modeling, diodes, field-effect transistors, Gaussian density-of-states

The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. / Master of Science

The thesis presents experimental studies of device characteristics and vibrational properties of atomic layer thin graphene and molybdenum disulphide (MoS2). We carried out Raman spectroscopic studies on field effect transistors (FET) fabricated from these materials to investigate the phonons renormalized by carrier doping thus giving quantitative information on electron-phonon coupling. Below, we furnish a synoptic presentation of our work on these systems. Chapter1: Introduction Chapter1, presents a detailed introduction of the systems studied in this the¬sis, namely single layer graphene (SLG), bilayer graphene (BLG) and single layer molybdenum disulphide (MoS2). We have mainly discussed their electronic and vibrational properties in the light of Raman spectroscopy. A review of the Raman studies on graphene layers is presented. Chapter2: Methodology and Experimental Techniques Chapter 2 starts with a description of Raman instrumentation. The steps for isolating graphene and MoS 2 flakes and the subsequent device fabrication procedures involving lithography are discussed in detail. A brief account of the top gated field effect transistor (FET) using solid polymer electrolyte is presented. Chapter3: Band gap opening in bilayer graphene and formation of p-n junction in top gated graphene transistors: Transport and Raman studies In Chapter3 the bilayer graphene (BLG) field effect transistor is fabricated in a dual gate configuration which enables us to control the energy band gap and the Fermi level independently. The gap in bilayer energy spectrum is observed through different values of the resistance maximum in the back gate sweep curves, each taken at a fixed top gate voltage. The gate capacitance of the polymer electrolyte is estimated from the experimental data to be 1.5μF/cm2 . The energy gap opened between the valence and conduction bands using this dual-gated geometry is es¬timated invoking a simple model which takes into account the screening of gate induced charges between the two layers. The presence of the controlled gap in the energy band structure along with the p-n junction creates a new possibility for the bilayer to be used as possible source of terahertz source. The formation of p-n junction along a bilayer graphene (BLG) channel is achieved in a electrolytically top gated BLG FET, where the drain-source voltage VDS across the channel is continuously varied at a fixed top gate voltage VT(VT>0). Three cases may arise as VDS is varied keeping VT fixed: (i) for VT-VDS0, the entire channel is doped with electron, (ii) for VT-VDS= 0, the drain end becomes depleted of carriers and kink in the IDS vs VDS curve appears, (iii) for VT-VDS « 0, carrier reversal takes place at the drain end, accumulation of holes starts taking place at the drain end while the source side is still doped with electrton. The verification of the spatial variation of carrier concentration in a similar top gated single layer graphene (SLG) FET device is done using spatially resolved Ra¬man spectroscopy. The signature 2D Raman band in a single layer graphene shows opposite trend when doped: 2D peak position decreases for electron doping while it increases for hole doping. On the other hand, the G mode response being symmetric in doping can act as a read-out for the carrier concentration. We monitor the peak position of the G and the 2D bands at different locations along the SLG FET channel. For a fixed top gate voltage V T , both G and the 2D band frequencies vary along the channel. For a positive VTsuch that VT-VDS= 0, the peak frequencies ωGand ω2DωG/2D occur at the undoped frequency (ωG/2D)n=0 near the drain end while the source end corresponds to non-zero concentration. When VT-VDS<0, Raman spectra from hole doped regions (drain end) in the channels show an blue-shift in ω2Dwhile from the electron doped regions (near source) ω2Dis softened. Chapter4: Mixing Of Mode Symmetries In Top Gated Bilayer And Multilayer Graphene Field Effect Devices In Chapter4, the effect of gating on a bilayer graphene is captured by using Raman spectroscopy which shows a mixing of different optical modes belonging to differ¬ent symmetries. The zone-center G phonon mode splits into a low frequency (Glow) and a high frequency (Ghigh) mode and the two modes show different dependence on doping. The two G bands show different trends with doping, implying different electron-phonon coupling. The frequency separation between the two sub-bands in¬creases with increased doping. The mode with higher frequency, termed as Ghigh, shows stiffening as we increase the doping whereas the other mode, Glow, shows softening for low electron doping and then hardening at higher doping. The mode splitting is explained in terms of mixing of zone-center in-plane optical phonons rep¬resenting in-phase and out-of-phase inter-layer atomic motions. The experimental results are combined with the theoretical predictions made using density functional theory by Gava et al.[PRB 80, 155422 (2009)]. Similar G band splitting is observed in the Raman spectra from multilayer graphene showing influence of stacking on the symmetry properties. Chapter5: Anomalous dispersion of D and 2D modes in graphene and doping dependence of 2D ′and 2D+G bands Chapter 5 consists of two parts: Part A titled “Doping dependent anomalous dispersion of D and 2D modes in graphene” describes the tunability of electron-phonon coupling (EPC) associated with the highest optical phonon branch (K-A) around the zone corner K using a top gated single layer graphene field effect transistor. Raman D and 2D modes originate from this branch and are dispersive with laser excitation energy. Since the EPC is proportional to the slope of the phonon branch, doping dependence of the D and 2D modes is carried out for different laser energies. The dispersion of the D mode decreases for both the electron and the hole doping, in agreement with the recent theory of Attaccalite et. al [Nano Letters, 10, 1172 (2010)]. In order to observe D-band in the SLG samples, low energy argon ion bombardment was carried out. The D peak positions for variable carrier concentration using top-gated FET geometry are determined for three laser energies, 1.96 eV, 2.41 eV and 2.54 eV. However, the dispersion of the 2D band as a function of doping shows an opposite trend. This most curious result is quantitatively explained us¬ing a fifth order process rather than the usual fourth order double resonant process usually considered for both the D and 2D modes. Part B titled “Raman spectral features of second order 2D’ and 2D+G modes in doped graphene transistor” deals with doping dependence of 2D’ and 2D+G bands in single layer graphene transistor. The phonon frequency blue shifts for the hole doping and whereas it red shifts for electron doping, similar to the behaviour of the 2D band. The linewidth of the 2D+G combination mode too follows the 2D trend increasing with doping while that of 2D’ mode remains invariant. Chapter6: New Raman modes in graphene layers using 2eV light Unique resonant Raman modes are identified at 1530 cm−1 and 1445 cm−1 in single, bi, tri and few layers graphene samples using 1.96 eV (633 nm) laser excitation energy (EL). These modes are absent in Raman spectra using 2.41 eV excitation energy. In addition, the defect-induced D band which is observed only from the edges of a pristine graphene sample, is observed from the entire sample region using E L = 1.96 eV. Raman images with peak frequencies centered at 1530 cm−1, 1445 cm−1 and D band are recorded to show their correlations. With 1.96 eV, we also observe a very clear splitting of the D mode with a separation of ∼32 cm−1, recently predicted in the context of armchair graphene nanoribbons due to trigonal warping effect for phonon dispersion. All these findings suggest a resonance condition at ∼2eVdue to homo-lumo gap of a defect in graphene energy band structure. Chapter7: Single and few layer MoS2: Resonant Raman and Phonon Renormalization Chapter 7 is divided into two parts. In Part A “Layer dependent Resonant Raman scattering of a few layer MoS2”, we discuss resonant Raman scattering from single, bi, four and seven layers MoS2. As bulk crystal of MoS2is thinned down to a few atomic layers, the indirect gap widens turning into a direct gap semiconductor with a band gap of 1.96 eV in its monolayer form. We perform Raman study from MoS 2 layers employing 1.96 eV laser excitation in order to achieve resonance condition. The prominent Raman modes for MoS 2 include first order E12g mode at ∼383 cm−1 and the A1gmode at ∼408 cm−1 which are observed under both non resonant and resonant conditions. A1gphonon involves the sulphur atomic vibration in opposite direction along the c axis (perpendicular to the basal plane) whereas for E12g mode, displacement of Mo and sulphur atoms are in the basal plane. With decreasing layer thickness, these two modes shifts in opposite direction, the E12g mode shows a blue shift of ∼2cm−1 while the A1gis red shifted by ∼4cm−1 . Under resonant condi¬tion, apart from E12g and A1gmodes, several new Raman spectral features, which are completely absent in bulk, are observed in single, bi and few layer spectra pointing out the importance of Raman characterization. New Raman mode attributed to the longitudinal acoustic mode belonging to the phonon branch at M along the Γ-M direction of the Brillouin zone is seen at ∼230 cm−1 for bi, four and seven layers. The most intense region of the spectrum around 460 cm−1 is characterized by layer dependent frequencies and spectral intensities with the band near 460 cm−1 becoming asymmetric as the sample thickness is increased. In the high frequency region between 510-630 cm−1, new bands are seen for bi, four and seven layers. In Part B titled “Symmetry-dependent phonon renormalization in monolayer MoS2transistor”, we show that in monolayer MoS2the two Raman-active phonons, A1g and E21 g, behave very differently as a function of doping induced by the top gate voltage in FET geometry. The FET achieves an on-off ratio of ∼ 105 for electron doping. We show that while E12g phonon is essentially unaffected, the A1gphonon is strongly influenced by the level of doping. We quantitatively understand our experimental results through the use of first-principles calculations to determine frequencies and electron-phonon coupling for both the phonons as a function of carrier concentration. We present symmetry arguments to explain why only A1g mode is renormalized significantly by doping. Our results bring out a quantitative under¬standing of electron-phonon interaction in single layer MoS2.

Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region.  This thesis presents an experimental investigation on the GBTs as well as integration process developments for the fabrication of graphene-based devices. In this work, a full device fabrication and graphene integration process were designed with high CMOS compatibility considerations. To this aim, basic process modules, such as graphene transfer, deposition of materials on graphene, and formation of tunnel barriers, were developed and optimized. A PDMS-supporting graphene transfer process were introduced to facilitate the wet/dry wafer-scale transfer from metal substrate onto an arbitrarily substrate. In addition, dielectric deposition on graphene using atomic layer deposition (ALD) was investigated. These dielectric layers, mainly, served as the base-collector insulators in the fabricated GBTs. Moreover, the integration of silicon (Si) on the graphene surface was studied. Using the developed fabrication process, the first proof of concept devices were demonstrated. These devices utilized 5 nm-thick silicon oxide (SiO2) and about 20 nm-thick aluminum oxide (Al2O3) as the emitter-base insulator (EBI) and base-collector insulator (BCI). The direct current (DC) functionality of these devices exhibited &gt;104 on/off current ratios and a current transfer ratio of about 6%. The performance of these devices was limited by the non-optimized barrier parameters and device manufacturing technology. The possibility to improve and optimize the GBT performance was demonstrated by applying different barrier optimization approaches. Comparing to the proof of concept devices, several orders of magnitude higher injection current density was achieved using a bilayer dielectric tunnel barrier. Utilizing the novel TmSiO/TiO2 (1 nm/6 nm) dielectric stack, this tunnel barrier prevents defect mediated tunneling and, simultaneously, promotes the Fowler-Nordheim tunneling (FNT) and step tunneling (ST). Furthermore, it was shown that Si/graphene Schottky junction can significantly improve the current gain by reducing the electron backscattering at the base-collector barrier. In this thesis, a maximum current transfer ratio of about 35% has been achieved. / <p>QC 20160503</p>

Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.