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Voltage-mode controlled synchronous DC-DC buck converter using 0.13[mu] CMOS switchesWolfe, Brandon Ward 27 February 2012 (has links)
This report is a study of the effects of a commercial 0.13[mu] process and automotive temperature corners on a synchronous DC-DC buck converter design. The basics of switching converters will be explored with an emphasis on voltage-mode controlled feedback. A Type-III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network. The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high-side PMOS and low-side NMOS transistor switches. After the synchronous buck converter design was complete, the effect of process and temperature on efficiency, output voltage ripple, inductor peak to peak current, and output voltage load response was examined. / text
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High Speed On-Chip Measurment Circuit / Inbyggd krets för höghastighetsmätning på chipStridfelt, Arvid January 2005 (has links)
<p>This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. </p><p>It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. </p><p>This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. </p><p>The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.</p>
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High Speed On-Chip Measurment Circuit / Inbyggd krets för höghastighetsmätning på chipStridfelt, Arvid January 2005 (has links)
This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.
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