<p>An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed,power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations,Ethernet, cable modems and high performance digital communication systems.Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the so-called post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correctionof these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture.The first seven stages are implemented using the 1.5-bit/stage architecture whilethe last stage is a one-bit flash ADC. The ADC and error correction algorithms simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency.</p>

Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters. In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second- stage analog-to-digital converter. In addition, this dissertation includes circuit design techniques that provide a digital offset correction for the comparator-based two-step structure, binary-weighted switching for an R-2R digital-to-analog converter, and reference trimming for a flash analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply. The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with an ENOB of 11.4 b, which is the lowest FOM in high-resolution analog-to-digital converters having greater than an ENOB of 10 b. Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research. / Graduation date: 2012

A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.

The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter. In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.

Det här arbetet handlar om att ta fram beteendemodeller av analog till digital omvandlare avsedda för tillämpningar i radiofrekvensområdet. Det gäller tillämpningar inom telekommunikation men även in test- och mätinstrument där omvandlingen från analoga till digitala signaler ofta är en prestandamässig flaskhals. Modellerna är avsedda att användas för att efterbehandla utdata från omvandlaren och på så sätt förbättra prestanda på den digitala signalen. Genom att skapa modeller av verkliga omvandlare och hur dessa avviker från ett idealt beteende kan ofullständigheter korrigeras genom så kallad postkorrigering. Beteendemodeller innebär att genererar en lämplig insignal, mäta utdata och beräkna en modell. För omvandlare i radiofrekvensområdet ställs höga krav på instrumentering. Den testutrustningen som används är baserad på moderna högprestanda instrument som har kompletterats med specialbyggd utrustning för signalkonditionering och datainsamling. I avhandlingen har även olika insignaler utvärderats med såväl teoretisk som experimentell analys. Det finns ett flertal olika varianter av modeller för att modulera ett olinjär, dynamisk system. För att få en parametereffektiv modell har utgångspunkten varit att utgå från en Volterramodell som på ett optimalt sätt beskriver svagt olinjära dynamiska system, så som analog till digital omvandlare, men som är alltför omfattande i antal parametrar. Volterramodellens har sedan reducerats till en mindre parameterintensiv, modellerstruktur på så sätt att Volterrakärnans symmetriegenskaper jämförts med symmetrierna hos andra modeller. En alternativ metod är att använda en Kautz-Volterramodell. Den har samma generella egenskaper som Volterramodellen, men är inte lika parameterkrävande. I den här avhandlingen redovisas experimentella resultat av Kautz-Volterramodellen som i framtiden kommer att vara intressanta att använda för postkorrigeringen. För att kunna beskriva beteenden som en dynamiska olinjära modellen inte klarar av har modellen kompletterats med en statisk styckvis linjär modellkomponent. I avhandlingen presenteras en sluten lösning för att identifiera samtliga paramervärden i modellen. Vidare har det i avhandlingen genomförs en analys av hur respektive komponent påverkar prestanda på utsignalen. Därigenom erhålls ett mått på den maximala prestandaförbättring som kan uppnås om felet kan elimineras. / This work considers behavior modeling of analog to digital converters with applications in the radio frequency range, including the field of telecommunication as well as test and measurement instrumentation, where the conversion from analog to digital signals often is a bottleneck in performance. The models are intended to post-process output data from the converter and thereby improve the performance of the digital signal. By building a model of practical converters and the way in which they deviate from ideal, imperfections can be corrected using post-correction methods. Behavior modeling implies generation of a suitable stimulus, capturing the output data, and characterizing a model. The demands on the test setup are high for converters in the radio frequency range. The test-bed used in this thesis is composed of commercial state-of-the-art instruments and components designed for signal conditioning and signal capture. Further, in this thesis, different stimuli are evaluated, theoretically as well as experimentally. There are a large number of available model structures for dynamic nonlinear systems. In order to achieve a parameter efficient model structure, a Volterra model was used as a starting-point, which can describe any weak nonlinear system with fading memory, such as analog to digital converters. However, it requires a large number of coefficients; for this reason the Volterra model was reduced to a model structure with fewer parameters, by comparing the symmetry properties of the Volterra kernels with the symmetries from other models. An alternative method is the Kautz-Volterra model, which has the same general properties as the Volterra model, but with fewer parameters. This thesis gives experimental results of the Kautz-Volterra model, which will be interesting to apply in a post-correction algorithm in the future. To cover behavior not explained by the dynamic nonlinear model, a complementary piecewise linear model component is added. In this thesis, a closed form solution to the estimation problem for both these model components is given. By gradually correcting for each component the performance will improve step by step. In this thesis, the relation between a given component and the performance of the converter is given, as well as potential for improvement of an optimal post-correction. / QC 20100629

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed,power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations,Ethernet, cable modems and high performance digital communication systems.Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the so-called post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correctionof these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture.The first seven stages are implemented using the 1.5-bit/stage architecture whilethe last stage is a one-bit flash ADC. The ADC and error correction algorithms simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency.

The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.The thesis initially focuses upon selection of suitable Analog to Digital Converter(ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power consumption.In second phase a mathematical model of a Time-Interleaved Successive ApproximationRegister (TI-SAR) ADC is developed which emulates the behavior ofSAR ADC in Matlab and the errors that are characteristic of the time interleavedstructure are modeled.In the third phase a behavioral model of TI-SAR ADC having 16 channels and12 bit resolution, is built using the top-down methodology in Cadence simulationtool. All the modules were modeled at behavioral level in Verilog-A. The functionalityof the model is verified by simulation using signal of 30 MHz and clockfrequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signalto Noise Distortion ratio) 74 dB is achieved.In the final phase two architectures of comparators are implemented in 65nmtechnology at schematic level. Simulation results show that SNDR of 71 dB isachievable with a minimal power consumption of 169.6 μWper comparator runningat 300 MHz.NyckelordKeywords

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture.  Based on this analysis, dynamic two-stage comparator is selected due to its energy efficiency and capability of working in low supply voltages. Eventually, based on these studies an ultra-low power 10-bit SAR ADC in 65 nm technology is designed. Simulation results predict that the ADC consumes 12.4nW and achieves an energy efficiency of 14.7fJ/conversion at supply voltage of 1V and sampling frequency of 1kS/s. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits. The ADC is functional down to supply voltage of 0.5V with proper performance and minimal power consumption of 6.28nW.