In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort. In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB. The design is simulated in UMC 0.18um technology in Cadence environment. The choice of technology is made as the target application for the ADC, 'X-ray Detector System' is designed in the same technology. The simulation results obtained in-term of ENOB and power consumption are satisfactory for the target application.

In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to convert the sensor output to digital data. The data is used to determine the necessary control signals to restore the performance of the power amplifier. The circuits have been designed and implemented in ST Microelectronics CMOS 90nm process.

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter. Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18??m CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10???s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter.

A ressonância magnética (RM) tem sido amplamente utilizada no diagnóstico por imagem de alterações de glândulas salivares. No entanto, a presença de aspectos similares nas imagens com técnicas convencionais de RM dificulta a distinção do diagnóstico entre patologias inflamatórias e neoplásicas. O objetivo deste estudo foi comparar valores dos coeficientes de difusão aparentes (ADC - Apparent Diffusion Coefficient) de imagem ponderada em difusão (DWI - Difusion Weighted Imaging) com ressonância magnética, entre glândulas salivares normais, casos com sialoadenite e com adenoma pleomórfico das glândulas salivares maiores. Vinte e dois pacientes (totalizando 44 glândulas salivares maiores) diagnosticados com sialoadenite unilateral (em glândula parótida ou submandibular) ou adenoma pleomórfico (apenas em parótida) foram selecionados. Todas as glândulas contralaterais não afetadas também foram analisadas. Imagens de RM ponderadas em T1, T2 e DWI foram obtidas utilizando sequências de pulso spin-eco (SE) com um aparelho de ressonância magnética de 1.5 Tesla. Primeiramente, a performance diagnóstica (sensitividade, especificidade e acurácia) foi calculada para três observadores após analisarem imagens de RM e DWI, separadamente. Em seguida, os valores médios de ADC foram comparados entre os três grupos analisados (glândulas normais contralateral, sialoadenite e adenoma pleomórfico). O uso da DWI rendeu uma melhor performance diagnóstica em geral para todos os observadores. Além disso, casos de adenoma pleomórfico apresentaram os maiores valores de ADC do estudo. Dentro das limitações deste estudo, os resultados sugerem que DWI permite a diferenciação entre sialoadenite e adenoma pleomórfico. / Alterations of the salivary glands are usually detected by conventional magnetic resonance imaging (MRI) techniques. However, their imaging presentation may present similar aspects. The aim of this study was to compare apparent diffusion coefficient (ADC) values from diffusion-weighted MRI (DWI) among normal salivary glands, cases with sialadenitis and with pleomorphic adenoma of major salivary glands. Twenty-two patients (totaling 44 major salivary glands) diagnosed with either unilateral sialadenitis (on either parotid or submandibular gland) or parotid gland pleomorphic adenoma were selected. Contralateral non-affected glands (normal) were also analyzed. DWI images were achieved using a spin-echo (SE) pulse sequence with a 1.5T MRI device. Mean ADC values were compared among the three groups analyzed (contralateral normal glands, sialadenitis and pleomorphic adenoma). Furthermore, diagnostic performance of MRI and DWI were calculated for three observers. DWI also presented better diagnostic performance results. In addition, cases of pleomorphic adenoma presented the highest ADC values of the study. Within the limitations of this study, the present results suggest that DWI allows for differentiation between parotid sialadenitis and pleomorphic adenoma.

Planck est un satellite de l'ESA lancé en 2009, qui avais pour mission de faire une carte de très grande précision du rayonnement fossile de l'Univers, afin de mieux comprendre comment il s'est formé. Cet objectif ambitieux nécessite un niveau de maîtrise extrême des effets instrumentaux. Cependant en cours de mission il s'est avéré que le composant responsable de la numérisation des données scientifiques introduisait un bisais important qui compromettait l'exploitation scientifique des données de l'instrument Planck/HFI. Ce travail décris comment ce biais a été compris et corrigé avec succès. Une analyse très poussée a été conduite sur les détecteurs du satellite, la chaine cryogénique embarquée et le composant de numérisation lui même. Ce qui a nécessité une méthodologie spécifique afin de télécharger les données nécessaire depuis le satellite avant sa fin de mission et son décommissionnement. / Planck is an ESA spacecraft launched in 2009, its mission goal was to map with an exquisite precision the first light of Universe, to help understanding how it has formed. This ambitious objective requires a very high level of control on the instrumental effects. During the mission, it has been found that the component responsible of the digitization of scientific data introduced an unexpectedly high bias effect, preventing full exploitation of data from the Planck/HFI instrument. The present work relates how this bias effect was understood and successfully corrected for. A very deep analysis of the spacecraft detectors, the cryogenic chain, and the digitization component has been performed, which required a specific methodology to gather data from the spacecraft before the end of the mission and its decommissioning.

No description available.

The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.

No description available.

With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI.

This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.