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Bakalauro darbas “EFFECTUS ZODIACUS” parodo, kaip galima sukurti kolekciją, panaudojant stilizuotus Zodiako ženklus. Pirmajame teorinio aprašo skyriuje nagrinėjamos su tema susijusios sąvokos. Išskiriama ženklų ir simbolių klasifikacija bei panaudojimo sritys. Aiškinama, kokią įtaką zodiakai, horoskopų prognozės daro žmonėms, kokie skirtingų šaltinių nurodomi šių ženklų panašumai ir skirtumai. Pateikiami Zodiako ženklų stilizacijų variantai. Antrajame skyriuje išanalizuojamos 12 Zodiako ženklų charakteristikos, nagrinėjamos interpretacijos aprangos dizainerių kūryboje. Trečiajame skyriuje aprašomas bakalauro kūrybinės dalies įvykdymas. Ketvirtajame - darbo ryšio su verslumu skyriuje, aptariamos sukurtos kolekcijos realizavimo galimybės, SSGG analizė. Pridedami penki priedai. Išanalizuota informacija apie Zodiako ženklus, kitų dizainerių kūrybą, leido sukurti originalią 22 modelių „pret a porter de luxe“ kolekciją „EFFECTUS ZODIACUS“. / Bachelor’s work “EFFECTUS ZODIACUS” shows, how we can create the collection, using stilysed signs of the Zodiac. In the first theoretical section, the notions related with the theme are analysed. It is separating the classification and using sections of signs and symbols. Also, it is explained, what influence of zodiacs, horoscopes’ forecasts is making to humans, what similarities and differences are between sources. The versions of Zodiac signs stylizations are introduced too. In the second section analyzed 12 Zodiac signs’ characteristics, the interpretations of in clothes designers creation works. There is described the conception of collection in the third- Bachelor’s creative part section. In the fourth- work connection with enterprise section, are discussing about the realization abbilities of created collection, SWOT analysis Five additions are added: In conclussion, this analysed information about Zodiac signs and other designers’ creation works, allows me to design the ready to wear deluxe “EFFECTUS ZODIACUS” collection of 22 models.

This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magnitude improvement over existing solutions restricted to using only one type computational domain. To that end, I have helped build large and complicated reconfigurable systems (and software tools for helping to use these systems) capable of implementing solutions to problems in all three of those domains simultaneously. These systems are used to explore and implement these cross domain solutions to difficult problems. The earlier work was involved with simply applying floating-gate technology to improving the building blocks of digital systems. Through that early work a new logic family built from floating-gate transistors was discovered, a Logical Effort compatible power analysis technique was developed, and low power floating-gate based FPGA was implemented. This work was then merged with existing research in the group involving solving problems using reconfigurable analog, and neuromorphic techniques. Thus converging on the mentioned systems that allow one to solve problems using techniques from all three domains: analog, neuromorphic, and digital.

In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long time operation. As a fundamental building block of ADC, comparator should support a tightened power budget. Therefore, developing low-power design techniques for comparator is becoming more and more important. As an alternative to the conventional voltage-mode comparator, this thesis proposed an energy efficient time-domain comparator, which uses digital circuits to process analog signals by representing them as timing information. The proposed time-domain comparator has three main features: comparing on both clock edges (rising/falling), asynchronous comparison and 2-bit/step comparison. With these features, power consumption of the comparator can be effectively reduced. For verification, the proposed time-domain comparator is fabricated in IBM 0.18um CMOS technology in comparison with other two conventional time-domain comparators working at 100kS/s sampling rate and 8-bit resolution. The achieved power consumption of the proposed time-domain comparator is 50nW, which is much lower than 84nW and 285nW of the other two time-domain comparators.

In Multi-Standard receivers, multiple radios co-exist in close proximity. A desired signal can be accompanied by significantly stronger out-of band interferers or blockers, which can severely degrade a receiver's sensitivity through gain compression of the blocks in the receiver chain. This work presents a new Transimpedance Amplifier (TIA) low-pass filter architecture which seeks to solve the out-of-band blocker problem of the existing architectures. A higher order filtering is embedded within the TIA in the form of an active feedback to provide more attenuation to out-of-band blockers. The active feedback circuitry feeds back an equivalent amount of current to the input node to cancel out incoming out-of-band blockers while maintaining an acceptable voltage swing at the output of the TIA. The proposed TIA filter has a channel bandwidth of 20MHz, and can processes interferers of +/- 10mA fully differential without saturating the opamps. The maximum single ended voltage swing at all the nodes is +/- 200mV. All the circuits were designed in IBM 180nm CMOS process with a supply voltage of 1.8V.