The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed load delay test (Launch-from-shift). Each method has its own drawbacks and many practical issues are associated with pattern generation and application. Our work focuses on the implementation and comparison of these transition fault testing techniques on multiple industrial ASIC designs. In this thesis, we present results from multiple designs and compare the two techniques with respect to test coverage, pattern volume and pattern generation time. For both methods, we discuss the effects of multiple clock domains, tester hardware considerations, false and multi-cycle paths and the implications of using a low cost tester. We then consider the implications of pattern volume on testing both stuck-at and transition faults and the effects of using transition fault patterns to test stuck-at faults. Finally, we present results from our analysis on switching activity of nets in the design, while executing transition fault patterns. / Master of Science

The proliferation of wireless communication devices in the recent past has increased the pressure on semiconductor manufacturers to produce quality radio frequency (RF) modules and systems at a low cost. This entails reducing their test cost as well, since the cost of testing modern RF devices can be up to 40% of their manufacturing cost. The high test cost of these devices can be mainly attributed to (a) the expensive nature of the RF automated test equipment (ATE) used to perform wafer-level and fully packaged RF functionality tests, (b) limited test point access for the application and capture of test signals, (c) the long test development and application times, and (d) the lack of diagnostic tools to evaluate and improve the performance of loadboards and test resources in high-volume tests. In this thesis, a framework for the efficient production testing of high-performance RF modules and systems using low-cost ATE is presented. This framework uses low-speed, low-resolution test resources to generate reliable tests for complex RF systems. Also, the test resources will be evaluated and improved ahead of high-volume tests to improve test yield and throughput. The components of the proposed framework are: (1) Genetic ATPG for reliable test stimulus generation using low-resolution test resources: A genetic algorithm (GA) based automatic test pattern generator (ATPG) to optimize the alternate test stimulus for reliable testing of complex RF systems using low-resolution, low-cost test resources. These test resources may be on-chip or off-chip. (2) Concurrent voltage/current alternate test methodology: A testing framework for efficiently testing the high-frequency specifications of RF systems using low-frequency spectral and/or transient current signatures. Suitable on-chip and/or off-chip design-for-test (DfT) resources are used to enable the source and capture operations at lower frequencies. (3) Loadboard checker: A checker tool to accurately characterize/diagnose the DfT resources on the RF loadboards used to enable test of RF devices/systems using low-cost ATE. (4) Advanced test signal processing algorithms: The performance of the low-cost ATE resources, in terms of their linearity/resolution, will be evaluated and improved to enable the accurate capture of the test response signals.

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.

Reversible logic computing is a rapidly developing research area. Both reversible logic synthesis and testing reversible logic circuits are very important issues in this area. In this thesis, we present our work in these two aspects. We consider a new fault model, namely the crosspoint fault, for reversible circuits. The effects of this kind of fault on the behaviour of the circuits are studied. A randomized test pattern generation algorithm targeting this kind of fault is introduced and analyzed. The relationship between the crosspoint faults and stuck-at faults is also investigated. The crosspoint fault model is then studied for possible applications in reversible logic synthesis. One type of redundancy exists in Toffoli networks in the form of undetectable multiple crosspoint faults. So redundant circuits can be simplified by deleting those undetectable faults. The testability of multiple crosspoint faults is analyzed in detail. Several important properties are proved and integrated into the simplifying algorithm so as to speed up the process. We also provide an optimized implementation of a Reed-Muller spectra based reversible logic synthesis algorithm. This new implementation uses a compact form of the Reed-Muller spectra table of the specified reversible function to save memory during execution. Experimental results are presented to illustrate the significant improvement of this new implementation.

Este trabalho tem como objetivo realizar um estudo do problema de teste de circuitos analógicos e mistos, propondo uma metodologia de teste e apresentando uma ferramenta para geração automática de vetores de teste (ATPG). A necessidade deste tipo de pesquisa torna-se clara no momento em que um número cada vez maior de aplicações requer algum tipo de interação entre dispositivos analógicos e digitais, não só em se tratando de placas de circuito impresso, mas também em um mesmo circuito integrado. A metodologia prevê a detecção de falhas paramétricas, de grandes desvios e catastróficas em circuitos lineares e não-lineares. Além disso. a ocorrência de falhas de interação é considerada, assim como a definição de vetores para diagnóstico que garantam máxima cobertura de falhas. Inicialmente são apresentados alguns aspectos teóricos relacionados ao teste deste tipo de circuitos (complexidade do teste, abordagens existentes e trabalhos correlatos). A seguir, são apresentados o modelo de falhas utilizado e a metodologia proposta, bem como a ferramenta de ATPG. A técnica é aplicada, então, a dois circuitos. O processo de geração dos vetores de teste é explicado e exemplos de vetores gerados são apresentados. Posteriormente, uma proposta de automatização do método é feita, acompanhada da descrição de algumas ferramentas comerciais utilizadas. Por fim, os resultados e conclusões são apresentados. / This work aims at studying the testing problems related to analog and mixedsignal circuits. This kind of research is very useful nowadays, since there is a great demand for circuits that need some kind of interaction between analog and digital blocks. This document presents a method and an automatic test pattern generation tool aplicable to the detection of soft, large and hard fault in linear and non-linear circuits. This method considers, also, interaction faults and computes diagnose vectors that garantee maximal fault coverage. At first. a brief review of methods. approaches and related works is presented. Then. the fault model used and the test methodology are defined. and an ATPG tool is proposed. Next, the ATPG algorithm is applied to a linear and to a non-linear circuit. The test vector generation process and the test vectors computed are then shown. After that a way to automatize the ATPG tool is discussed under the light of those commercial tools that were used in this work. Finally. the conclusions and results are presented.

Este trabalho tem como objetivo realizar um estudo do problema de teste de circuitos analógicos e mistos, propondo uma metodologia de teste e apresentando uma ferramenta para geração automática de vetores de teste (ATPG). A necessidade deste tipo de pesquisa torna-se clara no momento em que um número cada vez maior de aplicações requer algum tipo de interação entre dispositivos analógicos e digitais, não só em se tratando de placas de circuito impresso, mas também em um mesmo circuito integrado. A metodologia prevê a detecção de falhas paramétricas, de grandes desvios e catastróficas em circuitos lineares e não-lineares. Além disso. a ocorrência de falhas de interação é considerada, assim como a definição de vetores para diagnóstico que garantam máxima cobertura de falhas. Inicialmente são apresentados alguns aspectos teóricos relacionados ao teste deste tipo de circuitos (complexidade do teste, abordagens existentes e trabalhos correlatos). A seguir, são apresentados o modelo de falhas utilizado e a metodologia proposta, bem como a ferramenta de ATPG. A técnica é aplicada, então, a dois circuitos. O processo de geração dos vetores de teste é explicado e exemplos de vetores gerados são apresentados. Posteriormente, uma proposta de automatização do método é feita, acompanhada da descrição de algumas ferramentas comerciais utilizadas. Por fim, os resultados e conclusões são apresentados. / This work aims at studying the testing problems related to analog and mixedsignal circuits. This kind of research is very useful nowadays, since there is a great demand for circuits that need some kind of interaction between analog and digital blocks. This document presents a method and an automatic test pattern generation tool aplicable to the detection of soft, large and hard fault in linear and non-linear circuits. This method considers, also, interaction faults and computes diagnose vectors that garantee maximal fault coverage. At first. a brief review of methods. approaches and related works is presented. Then. the fault model used and the test methodology are defined. and an ATPG tool is proposed. Next, the ATPG algorithm is applied to a linear and to a non-linear circuit. The test vector generation process and the test vectors computed are then shown. After that a way to automatize the ATPG tool is discussed under the light of those commercial tools that were used in this work. Finally. the conclusions and results are presented.

Este trabalho tem como objetivo realizar um estudo do problema de teste de circuitos analógicos e mistos, propondo uma metodologia de teste e apresentando uma ferramenta para geração automática de vetores de teste (ATPG). A necessidade deste tipo de pesquisa torna-se clara no momento em que um número cada vez maior de aplicações requer algum tipo de interação entre dispositivos analógicos e digitais, não só em se tratando de placas de circuito impresso, mas também em um mesmo circuito integrado. A metodologia prevê a detecção de falhas paramétricas, de grandes desvios e catastróficas em circuitos lineares e não-lineares. Além disso. a ocorrência de falhas de interação é considerada, assim como a definição de vetores para diagnóstico que garantam máxima cobertura de falhas. Inicialmente são apresentados alguns aspectos teóricos relacionados ao teste deste tipo de circuitos (complexidade do teste, abordagens existentes e trabalhos correlatos). A seguir, são apresentados o modelo de falhas utilizado e a metodologia proposta, bem como a ferramenta de ATPG. A técnica é aplicada, então, a dois circuitos. O processo de geração dos vetores de teste é explicado e exemplos de vetores gerados são apresentados. Posteriormente, uma proposta de automatização do método é feita, acompanhada da descrição de algumas ferramentas comerciais utilizadas. Por fim, os resultados e conclusões são apresentados. / This work aims at studying the testing problems related to analog and mixedsignal circuits. This kind of research is very useful nowadays, since there is a great demand for circuits that need some kind of interaction between analog and digital blocks. This document presents a method and an automatic test pattern generation tool aplicable to the detection of soft, large and hard fault in linear and non-linear circuits. This method considers, also, interaction faults and computes diagnose vectors that garantee maximal fault coverage. At first. a brief review of methods. approaches and related works is presented. Then. the fault model used and the test methodology are defined. and an ATPG tool is proposed. Next, the ATPG algorithm is applied to a linear and to a non-linear circuit. The test vector generation process and the test vectors computed are then shown. After that a way to automatize the ATPG tool is discussed under the light of those commercial tools that were used in this work. Finally. the conclusions and results are presented.

Prokaryotic cells such as Escherichia coli use glucose as their preferred carbon source. In the absence of glucose, these cells resort to other sources to generate glucose and this process of de novo synthesis of glucose is termed gluconeogenesis. Phosphoenolpyruvate carboxykinase (Pck) is one of the three enzymes important in regulating gluconeogenesis. It converts oxaloacetic acid (OAA) from the Krebs cycle to phosphoenolpyruvate (PEP), a glycolytic intermediate. The Pck structural gene (pckA) is regulated by catabolite repression. There is a 100-fold induction of pckA-lacZ fusions at the onset of stationary phase concurrent with induction of glycogen synthesis. Mutants affecting the expression of pckA were analysed to shed some light on the mechanism of its genetic regulation.<p>Spontaneous mutants isolated with Pck- (lack of PEP carboxykinase activity) and Suc- (inability to utilise succinate as carbon source) phenotypes were previously characterised as atpG mutants defective in the ã subunit of ATP synthase.<p>In this work we find by reverse transcriptase and real time quantitative PCR that levels of pckA mRNA are normal in the atpG mutants and that the defects in expression of pckA are therefore likely at the level of translation, protein assembly and/or protein degradation. As expected, ATP synthase activity and proton pumping in inside-out membrane vesicles were defective in these atpG mutants. It is likely that one of these defects is affecting regulation or expression of the pckA gene. It was observed that atpG mutants were defective in calcium-dependent transformation although they could be made competent for electroporation. The atpG mutants were also defective for growth of P1 bacteriophage although they could serve as recipients for P1-dependent generalised transduction. These latter phenotypes are also likely due to defects in energy metabolism.

Prokaryotic cells such as Escherichia coli use glucose as their preferred carbon source. In the absence of glucose, these cells resort to other sources to generate glucose and this process of de novo synthesis of glucose is termed gluconeogenesis. Phosphoenolpyruvate carboxykinase (Pck) is one of the three enzymes important in regulating gluconeogenesis. It converts oxaloacetic acid (OAA) from the Krebs cycle to phosphoenolpyruvate (PEP), a glycolytic intermediate. The Pck structural gene (pckA) is regulated by catabolite repression. There is a 100-fold induction of pckA-lacZ fusions at the onset of stationary phase concurrent with induction of glycogen synthesis. Mutants affecting the expression of pckA were analysed to shed some light on the mechanism of its genetic regulation.<p>Spontaneous mutants isolated with Pck- (lack of PEP carboxykinase activity) and Suc- (inability to utilise succinate as carbon source) phenotypes were previously characterised as atpG mutants defective in the ã subunit of ATP synthase.<p>In this work we find by reverse transcriptase and real time quantitative PCR that levels of pckA mRNA are normal in the atpG mutants and that the defects in expression of pckA are therefore likely at the level of translation, protein assembly and/or protein degradation. As expected, ATP synthase activity and proton pumping in inside-out membrane vesicles were defective in these atpG mutants. It is likely that one of these defects is affecting regulation or expression of the pckA gene. It was observed that atpG mutants were defective in calcium-dependent transformation although they could be made competent for electroporation. The atpG mutants were also defective for growth of P1 bacteriophage although they could serve as recipients for P1-dependent generalised transduction. These latter phenotypes are also likely due to defects in energy metabolism.

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.