京都大学 / 0048 / 新制・課程博士 / 博士(医学) / 甲第22638号 / 医博第4621号 / 新制||医||1044(附属図書館) / 京都大学大学院医学研究科医学専攻 / (主査)教授 武藤 学, 教授 小川 誠司, 教授 小川 修 / 学位規則第4条第1項該当 / Doctor of Medical Science / Kyoto University / DFAM

Due to the increase in volume and speed of data transmissions in recent years, the demand for high-speed satellite communication solutions has increased. This thesis investigates the possibility of making a receiver for satellite radio based on an Analog Devices ADC evaluation board. To do this, evaluation boards for each component were acquired and tested individually before connecting them. The system components include an I/Q demodulator, a local oscillator, and an ADC. Using these components a system design for the radio receiver has been proposed, and its performance analyzed. The SNR of the designed system was measured to26 dB. This performance was deemed to be sufficient for a signal using the BPSKmodulation scheme.

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The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often target portable applications. Analog to digital conversion based on Delta Sigma modulation offers an optimal solution to the above problems. It is based on digital signal processing theory and offers benefits such as small footprint, high precision, noise de-sensitivity, and low power consumption. This thesis presents a methodology for designing low power Delta Sigma modulators using a combination of modern circuit design techniques. The developed techniques have resulted in several modulators that satisfy the initial design parameters. We applied this method to design three different modulators in the 0.35um digital CMOS technology with a 3.3V supply voltage. A first order Self-Referenced modulator has a resolution of 8 bits and the lowest power consumption at 75 uW. The most successful design is the second order Self Referenced modulator that produces 12 bits of resolution with a power consumption of 87 uW. A second order Floating Gate modulator possesses features for high noise rejection, and produces 10 bits of resolution while consuming 276 uW. It is concluded that self-referenced modulators dissipate less power and offer higher performance as compared more complicated circuits such as the floating gate modulator. / Master of Science

A ressonância magnética (RM) tem sido amplamente utilizada no diagnóstico por imagem de alterações de glândulas salivares. No entanto, a presença de aspectos similares nas imagens com técnicas convencionais de RM dificulta a distinção do diagnóstico entre patologias inflamatórias e neoplásicas. O objetivo deste estudo foi comparar valores dos coeficientes de difusão aparentes (ADC - Apparent Diffusion Coefficient) de imagem ponderada em difusão (DWI - Difusion Weighted Imaging) com ressonância magnética, entre glândulas salivares normais, casos com sialoadenite e com adenoma pleomórfico das glândulas salivares maiores. Vinte e dois pacientes (totalizando 44 glândulas salivares maiores) diagnosticados com sialoadenite unilateral (em glândula parótida ou submandibular) ou adenoma pleomórfico (apenas em parótida) foram selecionados. Todas as glândulas contralaterais não afetadas também foram analisadas. Imagens de RM ponderadas em T1, T2 e DWI foram obtidas utilizando sequências de pulso spin-eco (SE) com um aparelho de ressonância magnética de 1.5 Tesla. Primeiramente, a performance diagnóstica (sensitividade, especificidade e acurácia) foi calculada para três observadores após analisarem imagens de RM e DWI, separadamente. Em seguida, os valores médios de ADC foram comparados entre os três grupos analisados (glândulas normais contralateral, sialoadenite e adenoma pleomórfico). O uso da DWI rendeu uma melhor performance diagnóstica em geral para todos os observadores. Além disso, casos de adenoma pleomórfico apresentaram os maiores valores de ADC do estudo. Dentro das limitações deste estudo, os resultados sugerem que DWI permite a diferenciação entre sialoadenite e adenoma pleomórfico. / Alterations of the salivary glands are usually detected by conventional magnetic resonance imaging (MRI) techniques. However, their imaging presentation may present similar aspects. The aim of this study was to compare apparent diffusion coefficient (ADC) values from diffusion-weighted MRI (DWI) among normal salivary glands, cases with sialadenitis and with pleomorphic adenoma of major salivary glands. Twenty-two patients (totaling 44 major salivary glands) diagnosed with either unilateral sialadenitis (on either parotid or submandibular gland) or parotid gland pleomorphic adenoma were selected. Contralateral non-affected glands (normal) were also analyzed. DWI images were achieved using a spin-echo (SE) pulse sequence with a 1.5T MRI device. Mean ADC values were compared among the three groups analyzed (contralateral normal glands, sialadenitis and pleomorphic adenoma). Furthermore, diagnostic performance of MRI and DWI were calculated for three observers. DWI also presented better diagnostic performance results. In addition, cases of pleomorphic adenoma presented the highest ADC values of the study. Within the limitations of this study, the present results suggest that DWI allows for differentiation between parotid sialadenitis and pleomorphic adenoma.

Développer un générateur de signal analogique efficace est un élément clés pour les BIST des circuits analogiques et mixtes afin de produire le stimulus de test approprié, et remplacer les générateurs de signaux externes couteux dans les protocoles de standard de test fonctionnel analogique et mixte. Dans cette optique, nous présentons dans cette thèse des stratégies différentes de génération de signal sinusoïdal, basées sur les techniques d’annulation d’harmonique, pour le design d’un synthétiseur embarqué de signal sinusoïdal à haute fréquence. Les générateurs proposés utilisent des circuits numériques pour produire un ensemble de signaux carrés déphasés. Ces signaux carrés sont pondérés et combinés en appliquant différentes stratégies d’annulation d’harmonique dans un convertisseur numérique-analogique simplifié. Le générateur sélectionné permet d’annuler toutes les harmoniques en dessous de la 11ème. De plus, une simple stratégie de calibration a été conçue pour compenser l’effet de mismatch et de la variation de process de fabrication sur l’efficacité de la technique d’annulation d’harmonique. La simplicité du circuit rend cette approche adaptable pour le BIST des circuits intégrés analogique et mixte. Les modèles comportementaux, les simulations électriques d’un design en 28nm FDSOI et les résultats expérimentaux sont fournis pour valider la fonctionnalité du générateur proposé. Les résultats obtenus montrent des performances du circuit calibré autour de 52dB de SFDR pour un signal généré à 166MHz. / One of the main key points to enable mixed-signal BIST solutions is the development of efficient on-chip analog signal generators that can provide appropriate test stimuli and replace costly external signal generators in standard analog and mixed-signal functional test protocols. In this line, we present in this thesis different sinewave generation strategies based on harmonic cancellation techniques to design a high-frequency on-chip sinusoidal synthetize. The proposed generators employ digital hardware to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using different harmonic cancellation strategies in a simplified current-steering DAC. The selected generator allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28nm FDSOI design and experimental results are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 52dB of SFDR for a generated sinusoidal signal at 166 MHz.

<p>In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.</p><p>In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB.</p><p>The design is simulated in UMC 0.18um technology in Cadence environment. The choice of technology is made as the target application for the ADC, 'X-ray Detector System' is designed in the same technology. The simulation results obtained in-term of ENOB and power consumption are satisfactory for the target application.</p>

<p>Many medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto a capacitor, either with a variable time, or a variable capacitor value, followed by a sample-and-hold and a voltage A/D converter. The penalty for achieving wide-dynamic-range with the above approach is power and circuit complexity. </p><p>We propose to use the unique properties of current-input continuous-time Delta-Sigma A/D converters to combine the photo-detector current-integration with simultaneous wide-dynamic-range A/D conversion, using programmable reference currents and programmable clock frequencies. </p><p>A programmable current-input wide-dynamic-range Delta-Sigma A/D converter is designed and fabricated using MOSIS AMI 1.5 um 5 V CMOS process. The programmable A/D converter test results exhibit a consistent 12-bit resolution over the programmability range of the reference-currents, from 17.2 nA to 4.4 uA. The supply-current varies from 60 uA to 240 uA, whereas the A/D converter sample-rates increase from 4 Samples/s to 1 kSamples/s, achieving an overall system-dynamic-range of 20-bits. </p><p>An RF-powered version is designed and fabricated using MOSIS ON 0.5 um 3 V CMOS process. It is designed to work at 128 Samples/s to 11.25 kSamples/s sample-rates, achieving 12-bit resolution with only 128 oversampling ratio. The A/D converter supply-current is designed to range from 10 uA to 70 uA to allow its integration with an RF-power source. The RF-powered version of the programmable Delta-Sigma A/D converter includes an on-chip voltage regulator that generates a stable 3 V DC-voltage, and consumes only 15 uA current.</p> / Dissertation