Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "

<p>The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.</p><p>Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.</p>

The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs. Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

This thesis explores the study and design of an all-digital VCO-based ADC in a 65 nm CMOS technology. As the CMOS process enters the deep submicron region, the voltage-domain-based ADCs begins to suffer in improving their performance due to the use of complex analog components. A promising solution to improve the performance of an ADC is to employ as many as possible digital components in a time-domain-based ADC, where it uses the time resolution of an analog signal rather than the voltage resolution. In comparison, as the CMOS process scales down, the time resolution of an analog signal has found superior than the voltage resolution of an analog signal. In recent years, such time-domain-based ADCs have been taken an immense interest due to its inherent features and their design reasons. In this thesis work, the VCO-based ADC design, falls under the category of time-based ADCs which consists of a VCO and an appropriate digital processing circuitry. The employed VCO is used to convert a voltage-based signal into a time signal and thereby it also acts as a time-based quantizer. Then the resulting quantized-time signal is converted into a digital signal by an appropriate digital technique. After different architecture exploration, a conventional VCO-based ADC architecture is implemented in a high-level model to understand the characteristic behaviour of this time-based ADC and then a comprehensive functional schematic-level is designed in reference with the implemented behavioural model using cadence design environment. The performance has been verified using the mixed-levels, of transistor and behavioural-levels due to the greater simulation time of the implemented design. ADC’s dynamic performance has been evaluated using various experiments and simulations. Overall, the simulation experiments showed that the design was found to reach an ENOB of 4.9-bit at 572 MHz speed of sample per second, when a 120 MHz analog signal is applied. The achieved peak performance of the design was a SNR of 40 dB, SFDR of 34 dB and an SNDR of 31 dB over a 120 MHz BW at a 1 V supply voltage. Without any complex building blocks, this VCO-based all-digital ADC design provided a key feature of inherent noise shaping property and also found to be well compatible at the deep submicron region.

No description available.

This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V. / text

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The advent of a new generation of analog to digital converters (ADC’s) provides the aerospace signal-conditioning engineer with many design advantages, trade-offs and challenges for their next generation of signal conditioning systems. These advantages include increased range, resolution, accuracy, channel-count and sampling rate. However, in order to capitalize on these advantages, it is important to understand the trade-offs involved and to specify these systems correctly. Trade-offs include: • Analog vs. Digital signal conditioning • Implementation issues such as 12-bits vs. 16-bits (or even 24-bits) • Topology issues such as multiplexers vs. multiple ADC’s • Filter-type selection • Sigma-Delta vs. Successive Approximation ADC’s. Specification challenges include: • Total DC error vs. gain and offset (and drift, excitation, DNL, crosstalk, etc.) • ENOB vs. SINAD (or THD, SNR or Noise) • Coherency issues such as filter phase distortion vs. delay This paper will discuss some of these aspects and attempts to produce a succinct specification for the next generation of airborne signal conditioning, while also outlining some of the lessons learned in developing the same.

In the field of exoplanetary sciences, high contrast imaging is crucial for the direct detection of, and answering questions about habitability of exoplanets. For the direct imaging of habitable exoplanets, it is important to employ low inner working angle (IWA) coronagraphs, which can image exoplanets close to the PSF. To achieve the full performance of such coronagraphs, it is crucial to correct for atmospheric dispersion to the highest degree, as any leakage will limit the contrast. To achieve the highest contrast with the state-of-the-art coronagraphs in the SCExAO instrument, the spread in the point-spread function due to residual atmospheric dispersion should not be more than 1 mas in the science band. In a traditional approach, atmospheric dispersion is compensated by an atmospheric dispersion compensator (ADC), which is simply based on model which only takes into account the elevation of telescope and hence results in imperfect correction of dispersion. In this paper we present the first on-sky closed-loop measurement and correction of residual atmospheric dispersion. Exploiting the elongated nature of chromatic speckles, we can precisely measure the presence of atmospheric dispersion and by driving the ADC, we can do real-time correction. With the above approach, in broadband operation (y-H band) we achieved a residual of 4.2 mas from an initial 18.8 mas and as low as 1.4 mas in H-band only after correction, which is close to our science requirement. This work will be valuable in the field of high contrast imaging of habitable exoplanets in the era of the ELTs.