As wireless communication is ever-evolving, demanding higher data speeds, the requirementsincrease for the ADC, and the requirements for the comparator, which is one of the mainbuilding blocks, increase as well. The primary purpose of the comparator is to compare twovoltage levels and provide a logic output. One significant advantage of dynamic comparatorsis that they are more power-efficient than traditional comparators. There exist many differentarchitectures for dynamic comparators. In this thesis, the most promising designs areoptimized and evaluated over various parameters, such as speed, noise, offset, and hysteresis,while minimizing power consumption. The thesis includes a traditional StrongARM-latch,a double tail, and four triple tail comparators. The StrongARM-latch was the most powerefficientdesign while all the parameters were within the requirements, which was unexpected.

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In this thesis, the design of a scaling-friendly continuous-time closed-loop voltage controlled oscillator (VCO) based Delta-Sigma analog to digital converter (ADC) is introduced. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly operational transconductance amplifiers (OTAs) and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses digital to analog converter (DAC) mismatches. The prototype ADC in 130 nm complementary metal-oxide-semiconductor (CMOS) occupies a small area of 0.03 mm² and achieves 66.5 dB signal to noise and distortion ratio (SNDR) over 2 MHz bandwidth (BW) while sampling at 300 MHz and consuming 1.8 mW under a 1.2 V power supply. It can also operate with a low analog supply of 0.7 V and achieves 65.8 dB SNDR while consuming 1.1 mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25 pJ/conversion-step and 0.17 pJ/conversion-step, respectively. / text

As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.

The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded. Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.

Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a first order passive loop-filter and (2) a - converter with a second order active loop-filter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs $0.53for mono audio and $0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).

<p>The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded.</p><p>Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.</p>

The demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash or successive approximation ADC techniques. The high-resolution, high-speed requirements can relatively easier be achieved using pipelined architecture ADC’s than other implementations of ADC’s of the same requirements. Because the stages work simultaneously, the number of stages needed to obtain a certain resolution is not constrained by the required throughput rate. Latency is a result of a multistage concurrent operation of any pipelined system. But luckily enough, latency isn’t considered to be a problem in many ADC applications. In this work, a 1.5-bit stage in the pipeline ADC is completely implemented including its two voltage comparators, a DAC with three possible output voltages, and a multiplying digital to analog (MDAC) blocks. Only ideal components were used for clocking operation. At the end of design, a total harmonic distortion (THD) of less than -70 dB was achieved. / text