Ένας από τους πιο ευρέως γνωστούς αλγορίθμους κρυπτογράφησης είναι ο AES (Advanced Encryption Standard). Το πρότυπο κρυπτογράφησης AES περιγράφει μια διαδικασία κρυπτογράφησης ηλεκτρονικής πληροφορίας βασισμένη στην λογική της κωδικοποίησης ομάδων δεδομένων με κάποιο μυστικό κλειδί. Μέχρι τον Μάιο του 2009, οι μόνες επιτυχημένες δημοσιευμένες επιθέσεις ενάντια στο πρότυπο AES ήταν επιθέσεις πλάγιου-καναλιού σε συγκεκριμένες εφαρμογές. Η βασική ιδέα των επιθέσεων πλαγίου καναλιού είναι ότι κάποιος μπορεί να παρατηρήσει έναν αλγόριθμο ο οποίος εκτελείται σε ένα σύστημα επεξεργασίας και να εξάγει μερικές ή πλήρεις πληροφορίες για την κατάσταση του αλγορίθμου ή το κλειδί. Ένας συγκεκριμένος τύπος επιθέσεων πλάγιου καναλιού, cache επιθέσεις, βασίζεται στην παρακολούθηση της συμπεριφοράς της μνήμης cache των συστημάτων (την μετακίνηση των δεδομένων μέσα και έξω από την μνήμη cache). Σε αυτή την διπλωματική αναπτύχθηκε ένα πρόγραμμα κρυπτογράφησης/αποκρυπτογράφησης AES και μελετήθηκε η συμπεριφορά διάφορων μνημών cache μέσω ενός προσομοιωτή επεξεργαστή (Simplescalar) κατά την διάρκεια εκτέλεσής του. Σκοπός της διπλωματικής εργασίας ήταν να δείξουμε ότι το κρυπτοσύστημα AES είναι ευάλωτο σε επιθέσεις πλαγίου καναλιού κρυφής μνήμης. / AES (Advanced Encryption Standard) is one of the most popular cryptographic algorithms. AES describes a process of electronic data encryption based on encrypting data using a secret key. Up to May 2009, the only successful published attacks against AES were side-channel attacks. The main concept of side-channel attacks is that someone can observe an algorithm that is being implemented in a system and gain information about the state of the algorithm or the secret key. One particular type of side-channel attacks, cache-based attacks, is based on observing the behavior of the system’s cache memory (tha data that moves in and out of the cache memory). In this thesis an algorithm AES (encryption/decryption) was developed and we examined the behavior of different cache memories using a simulator (Simplescalar) while this algorithm was processing trying to figure out if AES is vulnerable to cache-based side channel attacks. This thesis shows if AES is vulnerable against cache-based side channel attacks.

The battery driven nature of wireless sensor networks, combined with the need of extended lifetime mandates that energy efficiency is a metric with high priority. In the current thesis we explore and compare the energy dissipation of di fferent processor architectures and how it is associated with performance and area requirements. The processor architectures are di erentiated based on the datapath length (16-bit, 32-bit, 64-bit and 128-bit) and the corresponding size of the data memories. Our study focuses on AES algorithm, and the indicated processor architectures support AES forward encryption, CCM (32/64/128), CBC (32/64/128) and CTR common modes of operation. In each processor architecture the instruction set is extended to increase the efficiency of the system. / -

Made available in DSpace on 2015-05-14T12:36:39Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 1849104 bytes, checksum: 222c0377ddf502eb4a6c7fd2f658bdb1 (MD5) Previous issue date: 2013-01-31 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This work addresses data encryption using Rijndael symmetric key encryption algorithm , which is used in Advanced Encryption Standard - AES. AES has massively widespread in computing, communications, and broadcast media applications, due to its robustness. By intensively using of all flavors and sizes of devices and networks, the AES has become the standard at the time of implementation and deployment of these applications when the major requirement, in addition to performance, is security, i.e. virtually all of those applications nowadays. In systems equipped with modern processors, even those on small devices, it is common to find some that perform the encryption and decryption procedures in software. With the "explosive" spread of addition of security layers in almost everything that is processed inside and outside of the devices, even on systems equipped with powerful computing resources, the possibility of performing these layers on (small) additional hardware resources, developed with specific purpose, has become attractive. This dissertation presents a study of the theoretical foundations involving AES, some architectures and implementations based on it and documented in the recent technical and scientific literature, as well as the methodologies and requirements for the development of its hardware implementation, in particular, focusing on mobile systems, where performance has to be achieved in low power consumption and small area scenarios. Reference models have been developed and functionally validated in high-level languages for each hierarchical architectural level compiled from the mentioned study. As a proof of concept, this work consisted in undertaking a project of an intellectual property of digital integrated circuit core (IP core) for the encryption/decryption procedures of AES, starting from the pseudocode level of the algorithms and going to the level of a digital integrated circuit core. Among the solutions studied from recent literature, modules and operations that could be replicated and/or reused were identified. A microarchitecture for the full AES was implemented hierarchically to the core level with standard cells placed and routed. The work also offers three implementation options for the block identified as the most complex: the S-Box. Results of performance and area were then presented and compared with those of literature. / Este trabalho aborda a criptografia de dados com chave simétrica com uso do algoritmo de criptografia Rijndael, que é utilizado no Advanced Encryption Standard - AES. Devido a sua robustez, tem se tornado massivamente difundido em aplicações computacionais, comunicação e de difusão de media. Abrangendo todos os tamanhos e sabores de dispositivos de rede, o AES tem sido o padrão na hora da implementação e disponibilização dessas aplicações quando o requisito principal, além do desempenho, é a segurança, ou seja, praticamente todas as aplicações digitais nos dias de hoje. Em sistemas de processamento dotados dos modernos processadores, mesmo os de pequeno porte, é comum encontrar sistemas que executam os procedimentos de criptografia e decriptografia em software. Com a proliferação "explosiva" da adição de camadas de segurança em quase tudo que é processado dentro e fora dos dispositivos, mesmo em sistemas dotados de poderosos recursos computacionais, tem se tornado atrativa a possibilidade de executar essas camadas em (pequenos) recursos adicionais de hardware, desenvolvidos com finalidade específica. Nesta dissertação, foram estudados os fundamentos teóricos, envolvendo o AES, arquiteturas e implementações documentadas na literatura técnica e científica recente, bem como as metodologias e requisitos específicos para fins de desenvolvimento de sua implementação em hardware, focando, em especial, os sistemas móveis, onde desempenho tem que ser conseguido com baixo consumo de energia e pouca área. Foram desenvolvidos e validados funcionalmente modelos de referência em linguagem de alto nível para cada nível de hierarquia arquitetural compilado do referido estudo. Como prova de conceito, este trabalho consistiu em realizar o projeto de uma propriedade intelectual de núcleo de circuito integrado IP-core, digital para realização dos procedimentos de criptografia/decriptografia do AES, partindo do nível do pseudocódigo dos algoritmos até o nível de um núcleo (core) de circuito integrado digital. Das soluções estudadas na literatura recente, foram identificados módulos e operações passíveis de serem replicadas/reusadas. Uma microarquitetura para o AES completo foi implementada hierarquicamente até o nível de núcleo com standard cells posicionado e roteado, contemplando ainda 3 opções de implementação para o bloco reconhecidamente o mais complexo: o S-Box. Resultados de desempenho e área foram apresentados e comparados.

This thesis is based on measuring how Relational Database Management Systems utilizing data-at-rest encryption with varying AES key lengths impact the performance in terms of transaction throughput of operations through the process of a controlled experiment. By measuring the effect through a series of load tests followed by statistical analysis, the impact of adopting a specific data-at-rest encryption algorithm could be displayed. The results gathered from this experiment were measured regarding the average transactional throughput of SQL operations. An OLTP workload in the benchmarking tool HammerDB was used to generate a transactional workload. This, in turn, was used to perform load tests on SQL databases encrypted with different AES-key lengths. The data gathered from these tests then underwent statistical analysis to either keep or reject the stated hypotheses. The statistical analysis performed on the different versions of the AES-algorithm showed no significant difference in terms of transaction throughput concerning the results gathered from the load tests on MariaDB. However, statistically, significant differences are proven to exist when running the same tests on MySQL. These results answered our research question, "Is there a significant difference in transaction throughput between the AES-128, AES-192, and AES-256 algorithms used to encrypt data-at-rest in MySQL and MariaDB?". The conclusion is that the statistical evidence suggests a significant difference in transactional throughput between AES algorithms in MySQL but not in MariaDB. This conclusion led us to investigate further transactional database performance between MySQL and MariaDB, where a specific type of transaction is measured to determine if there was a difference in performance between the databases themselves using the same encryption algorithm. The statistical evidence confirmed that MariaDB vastly outperformed MySQL in transactional throughput.

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.