This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

We consider the boundary control problem to stabilize the power of a signal and a pump propagating down a Raman amplifier. This is essentially an initial-boundary value problem (IBVP) of a hyperbolic system with Lotka-Volterra type nonlinearities. We treat the system as a control problem with states in the function space and use Lyapunov-based analysis to demonstrate asymptotic stability in the C_0 and the L_2-sense. The stability conditions are derived for closed-loop systems with a proportional controller and a dynamic controller, and confirmed by simulations in MATLAB.

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

We consider the boundary control problem to stabilize the power of a signal and a pump propagating down a Raman amplifier. This is essentially an initial-boundary value problem (IBVP) of a hyperbolic system with Lotka-Volterra type nonlinearities. We treat the system as a control problem with states in the function space and use Lyapunov-based analysis to demonstrate asymptotic stability in the C_0 and the L_2-sense. The stability conditions are derived for closed-loop systems with a proportional controller and a dynamic controller, and confirmed by simulations in MATLAB.

No description available.

The trade-off between linearity and efficiency is the key limiting factor to wideband power amplifier design. Current wireless research focuses much of its effort on building power amplifiers with the two aforementioned criteria going hand in hand to build an optimal design. This thesis investigates the sources of nonlinearity associated with GaN high electron mobility transistors (HEMT), and their subsequent effects on the linearity metrics of the power amplifier. The investigation began with an analysis of the sources of nonlinearity, and then a design-based approach to mitigate those sources of nonlinearity was developed. This design approach was compared with existing trends in power amplifier design. The device technology used in the design was CREE GaN HEMT (45W and 6W). In this report, a systematic approach to designing a two stage power amplifier is discussed, and analyzed for design of linear and highly efficient power amplifiers for base stations. The designed power amplifier consists of two stages: a driver stage and a power stage. The driver stage aimed to linearize the power stage by using circuit analysis and transistor properties along with providing the necessary gain. The power stage was built to complement the driver stage and to achieve high efficiency for the power amplifier. An inter-stage matching network placed between the two stages allowed for the required matching of impedances; transmission lines in the bias feed controlled the harmonic impedances for optimal performance without disrupting performance at fundamental frequencies. This approach effectively improved, and maintained, high efficiency over 200MHz of bandwidth. The design approach was simulated and fabricated in order to test the feasibility of linear power amplifier operation with the use of digital pre-distortion (DPD). The fabricated prototype achieved about 70% peak efficiency over the bandwidth and maintained linearity above 40dBc adjacent channel leakage ratio (ACLR) and below 3% error vector magnitude (EVM). The measurement results indicated that the need for DPD was eliminated when the power amplifier was operating in back-off at the center frequency (800MHz). This thesis compares the prototyped design with existing multistage designs which use linear drivers. The report provides conclusions derive from measurement results and bandwidth limitations faced throughout the course of the design. Lastly, potential research directions, which may allow researchers to overcome the limitations of this design, are discussed.

Esta investigación está conducida a la resolución del problema de encontrar soluciones rentables para el despliegue de redes de fibra hasta el hogar (Fibre to the Home - FTTH). En una red de FTTH, el equipo transmisor-receptor de usuario así como el despliegue de la fibra en la llamada 'última milla' son las barreras principales. Una topología que consiste en hacer llegar una única fibra para dirigirse a cada usuario reduce la cantidad de fibra requerida. Por otro lado, los componentes ópticos pasivos alivian los requisitos de mantenimiento de la red de acceso. El efecto del backscattering de Rayleigh se ha identificado como la interferencia más crítica de este tipo de transmisión, el efecto sobre el funcionamiento del sistema y las investigaciones de posibles soluciones al mencionado problema son centro de estudio de esta tesis. Los experimentos realizados, revelan que, a pesar de la interferencia causada por del effecto Rayleigh no se puede eliminar totalmente, hay diferentes técnicas capaces de atenuar dicho efecto. El uso de los amplificadores ópticos semiconductores para implementar las funciones de transmisión-recepción agrega simplicidad al diseño de red en términos de transparencia de la longitud de onda y gracias a las capacidades de la amplificación de esta familia de dispositivos.Los resultados experimentales presentaron en este trabajo demuestran con éxito la modulación y la detección a 1Gbit/s y 2.5Gbit/s con los dispositivos basados en semiconductores, en enlaces de hasta 30km e incluso de hasta 50km de longitud. Nuevos prototipos son potencialmente capaces de transmitir a 10Gbit/s. Estructuras reflectoras basadas en amplificadores ópticos semiconductores reflectores son los candidatos mas adecuados.Éstos, realizan funciones de transmisión eficientemente y proporcionan la amplificación adecuada. Sin embargo, es necesario el diseño de nuevos diseños capaces de transmitir datos a una velocidad mayor. Una estrategia de comunicación bidireccional mediante una única fibra es la arquitectura más interesante los términos de reducción de costes por usuario (CAPEX). Por estos motivos, la ONU se convierte en un elemento clave en redes de acceso y un área muy interesante de investigación. Para una evolución exitosa de FTTH el diseño de la unidad de red debe ser simple, robusto, flexible y bajo coste para el cliente final. La traducción de los requisitos anteriormente mencionados en especificaciones técnicas establece las pautas siguientes para el diseño del FTTH ONU- Una única fibra por cada usuario para reducir tamaño de la red de acceso- Independencia de la longitud de onda para permitir una operación transparente en redes WDM- Que no haya fuente de luz activa en las dependencias de usuario para prevenir el mantenimiento en el lado del usuario- Con amplificación y así poder aumentar el número de usuarios y alcanzar mayores distanciasDe esta manera, el objetivo principal de esta tesis es la investigación de unidades ópticas de red reflectoras, especialmente las basadas en amplificadores ópticos de semiconductor, así como su funcionamiento en redes de FTTH, basadas en tecnología de acceso WDM-PON. Esto implica fundamentalmente- Identificar arquitecturas y dispositivos propuestos por medio de la investigación del trabajo publicado relacionado y destacar limitaciones y requisitos de los sistemas actuales- evaluar las diversos alternativas para la ONU y para proponer soluciones mejoradas, demostradas con simulaciones y experimentos - investigar limitaciones posibles de los sistemas transmisión bidireccionales y desarrollar soluciones para la mejora de la transmisión- desarrollar descripciones analíticas de las señales implicadas en la transmisión / This research was conducted to deal with the problem of finding cost-effective solutions for Fibre-to-the-Home (FTTH) network deployment. In the FTTH network, the transceiver at the user premises and the deployment of fibre at the last mile are the major barriers. A single-fibre topology to address each user reduces the amount of fibre required; passive optical components alleviate maintenance requirements in the access network.The Rayleigh backscattering effect is identified as the most critical crosstalk in such transmission, the effect on the system performance and the investigations of possible solutions are presented in this thesis. The studies reveal that despite the Rayleigh backscattering crosstalk can not be totally eliminated, several techniques can mitigate the effect.The use of the semiconductor optical amplifiers to feature transceiver tasks at the user premises adds simplicity to the network design in terms of wavelength transparency and amplification capabilities. We propose implementations with semiconductor amplifiers and test modulation and detection potentials inside the optical network. The experimental results successfully demonstrate modulation and detection at 1Gbit/s and 2.5Gbit/s with semiconductor-based devices, in links of 30km and even though of 50km length; bit rate of 10Gbit/s is feasible with novel prototypes as well. Reflective structures based on reflective semiconductor optical amplifiers are potential candidates, as they perform transmission functions efficiently and provide adequate amplification however, it is necessary the design of further structures capable of transmitting at a higher bit rates.

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

This thesis starts with a discussion of different classes of operation of power amplifiers (PAs). Comparing advantages and disadvantages of these classes, class AB is chosen as the best initial candidate for the design of broadband PA. Different methods for design of matching networks are first discussed. Some of them fall into the group of narrowband matching networks, while others are suitable for a broadband context. Broadband design methodologies are categorized into two groups of real-to-real transformations and complex-to-real transformations. Complex-to-real transformations are the most useful methods for this project, since design of power amplifiers deals with complex loads rather than just real loads. The design of broadband matching networks exploiting filter theory is presented in this thesis for synthesizing broadband and highly efficient power amplifiers (PAs). Starting with sets of optimum impedances over the targeted frequency band, the matching networks are designed using a systematic approach. The effects of load termination at the 2nd and 3rd harmonic on the PA performance (efficiency) are studied. The significance of proper termination, especially at the 2nd harmonic, is highlighted. To prevent further complication of the design process, though, specific harmonic termination (stubs) is avoided and special arrangement of the matching network (position of the bias network) is preferred, as it is found to lead to acceptable efficiency. Two PA prototypes were designed with the proposed methodology using 25W GaN devices. The designs targeted two frequency bands: 1.8 to 2.2 GHz (20% BW) and 1.8 to 2.7 GHz (40% BW). For the former, drain efficiency (DE) of 70% (+/–5%) and output power of 45.5 dBm (+/- 1.0dB) was measured while the latter achieved very promising efficiency of about 60% over the entire bandwidth.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.