Magnetic Resonance Imaging (MRI) is a non-invasive procedure used in the medical community as a powerful way of creating images of the human anatomy. MRI is preferred over other examination techniques such as X-ray computed tomography (CT) because of its excellent soft tissue discrimination as well as the absence of ionizing radiation. Currently most clinical MRI systems use the single radio frequency coil imaging. However over past several years research has increasingly focused on the concept of using arrays of mutually decoupled surface coils. These surface coil arrays can simultaneously acquire multiple images, resulting in an increase in the field of view. This thesis pursues the design and construction of a high impedance preamplifier with the goal of investigating the decoupling of a surface coil array in a 4.7T magnetic resonance system.

É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos. / A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

This dissertation outlines the study and development of a Solid-state Impact-ionization Multiplier (SIM). The SIM is a stand-alone current amplifier designed with optical detection systems in mind. The SIM amplifies signals utilizing impact ionization as a source of gain. The SIM is fabricated on silicon in order to take advantage of its favorable impact ionization coefficients. Utilizing silicon in impact ionization based gain devices makes low noise and high gains attainable. Because it is a stand-alone device, it can be wired to an arbitrary current source making it capable of receiving an input from photodiodes of any material. This makes it possible to amplify a signal from a photodiode that has been optimized for a given wavelength. In this way, the SIM attempts to separate the absorption and multiplication portions in modern day optical detection/amplification devices such as in Avalanche Photodiodes (APDs). This flexibility allows it to be utilized in many different systems. The SIM has gone through several iterations in the last few years. Each change has been with the purpose of increasing gain, frequency response or yield. The progression of the device has come at the hand of much thought, theory, simulation, fabrication, and testing. One of the challenges encountered in its development has been gain controllability due to poor carrier confinement and premature breakdown. Increased gain control was developed through simulation and fabrication of a confining oxide layer. Yield and difficulties in consistent fabrication were also addressed by altering the input metallization and doping processes. The frequency response of the device has been the largest challenge in device development. Issues such as space charge, floating node voltage, edge effects and low signal amplification have caused limitations. Successes and attempts at overcoming these, and other, challenges is the basis of this dissertation of work.

This thesis focuses on the characterization and optimization of microwave power transistors using a commercial on-wafer harmonic load pull system. Specific attention is paid to the output tuning of the second harmonic impedance presented to the device. The ability to quantify the level of accuracy in a load pull system is explored by using various calibration validation methods, including a method called Delta-Gt. In this work experiments and simulation comparisons are described for three different device technologies, namely GaAs pHEMT, GaAs HJFET and InGaP HBT. Externally supplied non-linear models were used for the simulations and these were exercised and compared against 2.45 GHz fundamental frequency measurements made as part of this work to first validate the models against IV, S-Parameter and fundamental load-pull data and finally to explore performance variations under 2nd harmonic impedance tuning. The measured harmonic load-pull data pointed to different guidance on how one would match the 2nd harmonic for best performance. With regard to the model validation/assessment work it was found that only in the case of the pHEMT did the available non-linear model provide a good fit to all the different types of measurement data, including 2nd harmonic tuning data. This model was then used to show that even though the 2nd harmonic tuning measurement had a limited maximum reflection coefficient of about 0.8. Simulated results showed that the worst case linearity condition occurred for the same reflection angle as that measured, but that the variation between worst-case and best case linearity under 2nd harmonic tuning grows considerably larger as the magnitude of the 2nd harmonic reflection coefficient approaches 1. A key aspect of the methodology presented in this work is that once a non-linear model is proved to be valid for harmonic tuning conditions it can be used to explore harmonic tuning-related design trade-offs under a much wider range of frequency and tuning conditions than can be practically explored with measurements alone.

<p>This work focuses on different kinds of Switch Mode Power Amplifiers (SMPAs) using LDMOS technologies. It involves a literature study of different SMPA concepts. Choosing the suitable class that achieves the high efficiency was the base stone of this</p><p>work. A push-pull class J power amplifier (PA) was designed with an integrated LC resonator inside the package using the bondwires and die capacitances. Analysis and motivation of the chosen class is included. Designing the suitable Input/Output printed circuit board (PCB) external circuits (i.e.; BALUN circuit, Matching network and DC</p><p>bias network) was part of the work. This work is done by ADS simulation and showed a simulated result of about 70% drain efficiency for 34 W output power and 16 dB gain at 2.14 GHz. Study of the losses in each part of the design elements is also included.</p><p>Another design at lower frequency (i.e.; at 0.94 GHz) was also simulated and compared to the previous design. The drain efficiency was 83% for 32 W output power and 15.4 dB Gain.</p>

The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter. In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.

This thesis aims to use a hybrid quadrature polar modulator (HQPM) for enhancing average efficiency of 3G mobile transmitter with power control. The HQPM consists of a quadrature modulator instead of a phase modulator in the polar modulator for processing the RF modulated carrier and a Class-S modulator for processing the envelope signal. In addition, the instantaneous magnitude of the quadrature modulated signal is propotional to the instantaneous envelope magnitude. As a result, the output feed-through and gain-compression phenomenon in the polar modulator can be improved. The digital baseband processor realized by FPGA can generate CDMA2000 1x baseband signal with excellent modulation accuracy. For enhancing the average transmit efficiency, the output PA is realized as Class-E design. But the Vdd/AM and Vdd/PM nonlinear effects of the Class-E PA distort the output signal. To solve this problem, a digital predistorter is presented to compensate the nonlinear distortions. The proposed HQPM-based transmitter can simultaneously achieve high efficiency and high linearity over a wide modulated output power range.

One of the most critical blocks in a wide-band continuous time sigma delta (CTSD) analog-to-digital converter (ADC) is the loop filter. For most loop filter topologies, the performance of the filter depends largely on the performance of the operational amplifiers (op-amps) used in the filter. The op-amps need to have high linearity, low noise and large gain over a wide bandwidth. In this work, the impact of op-amp parameters like noise and linearity on system level performance of the CTSD ADC is studied, and the design specifications are derived for the op-amps. A new class-AB bias scheme, which is more robust to process variations and has an improved high frequency response over the conventional Monticelli bias scheme, is proposed. A biquadratic filter which forms the input stage of a 5th order low pass CTSD ADC is used as a test bench to characterize the op-amp performance. The proposed class-AB output stage is compared with the class-AB output stage with Monticelli bias scheme and a class-A output stage with bias current reuse. The filter using the new op-amp architecture has lower power consumption than the other two architectures. The proposed class AB bias scheme has better process variation and mismatch tolerance compared to the op-amp that uses conventional bias scheme.

A groundbased instrument to measure the Atmospheric airglow of the molecular oxygen infrared atmospheric band emission was designed, built, tested and operated. The two channel photometer constructed was based on the original design by Evans (1967) that had been used in balloon experiments. The two channel photometer system specifications are presented. The major difference between the presented design and the earlier two channel photometers is the detector. An Indium Gallium Arsenide (InGaAs) photodiode provided better signal to noise in the conversion of the infrared light signal to an electronic signal than the previously used Lead Sulphide (PbS) detectors. The completed instrument was tested to determine its performance characteristics. Through these tests it was found that the photometer output offset is sensitive to ambient temperature fluctuations. An analysis of the instrument noise was done in an attempt to explain this sensitivity. The output noise performance was characterized and is presented together with the absolute brightness and wavelength calibrations. Data was collected with the instrument in Saskatoon, SK and Eureka, NU. After an initial observation campaign in the high arctic (Eureka, NU) modifications were made to the environmental housing of the instrument in order to improve the scientific value of the data collected. The collected data was processed and a simple analysis performed to demonstrate the capability of the photometer to measure the infrared atmospheric airglow. The collected data can be used to determine the mesospheric ozone height profile. The required data analysis to do so is beyond the scope of this presentation. However, the presented data does demonstrate that the designed and constructed two channel photometer can make the necessary measurements.