Abstract During the last decade, the maximum capacity of an optical fiber transmission line more than doubled every year to match the fast-growing communication need. The technology break through in dry fiber fabrication opens the possibility for fiber bandwidth all the way from 1.3

Class D power amplifier applies in high efficiency circuit. In hearing aid system, we require high power efficiency, low-voltage and low-power. The operation of frequency is low frequency. All the circuits are designed based on the TSMC 035 CMOS process technology. The supply voltage is 1.5V and the input signal is 4KHz. Simulation results show that the Class D power efficiency is high efficiency amplifier. When 0.3V of 2KHz input signal is applied, The maximum THD is 0.63% and static current is 4uA and the efficiency is 83.6%.

Pulling bulk crystal into fiber is suitable for laser, amplified spontaneous emission (ASE), and optical amplifier applications in optical communications because of its structural similarity to silica fiber. Moreover, fiber configuration can confine pump light in a small cross-sectional area with a high energy density for a long distance. Among crystal fiber growth techniques, the laser-heated pedestal growth method (LHPG) was adopted. It is crucible free and can therefore produce high-purity, low-defect-density single crystals. However, interface loss of the crystal fiber is one of the main causes of optical loss. In order to reduce the optical loss, a proper method to clad the fiber is important for high device performance. For laser application, high-efficient Nd:YAG lasers were demonstrated using gradient-index crystal fibers. We used controlled profile of the active ion resulted in index difference of 0.0284 between the center and the edge of the fiber to confine the laser beam in the center region and thus reduced the interface loss. A laser output power of 80 mW was achieved with a slope efficiency of 28.9%, which, to our knowledge, is the highest ever achieved for diode-laser-pumped Nd:YAG fiber laser. For ASE and optical amplifier applications, Cr4+:YAG crystal fiber was studied due to its fluorescent spectrum just covering the low loss window of silica optical fiber. To reduce the fiber diameter and propagation loss, a novel cladding technique, codrawing LHPG (CDLHPG), was developed. Although fused-silica-clad fiber can be made with a 29-micron-diameter core and a propagation loss of less than 0.1 dB/cm, which is a factor of 7 smaller than that of an unclad fiber, it has almost no Cr4+ fluorescence in the core area due to the entering of SiO2 in YAG. With proper controlled growth parameters of the CDLHPG method, a double-clad fiber with a core diameter of 25 micron was successfully grown. Up to 2.36 mW of ASE with a bandwidth of 265 nm was demonstrated. After splicing the double-clad fiber with conventional single mode fiber, we successfully demonstrated the first transition metal-doped fiber amplifier in the optical fiber communication band. Up to 16-dB of gross gain at 1.47 micron was achieved.

The primary advantage of Class D amplifier is high power efficiency (typically >90%). However, there are two problems in open-loop Class D design: Total Harmonic Distortion (THD) and output dc static current (the power efficiency will be degraded). The THD is rising from non-ideal sample carrier in Pulse Width Modulation circuit, and output dc static current is due to the non-match transfer characteristic in output stage. For designer to have such problems will be a large load. To improve these two problems, we proposed a Class D power amplifier with passive feedback design. Simulation and Measurement results show that the power efficiency is higher than 90% at 250Hz ~ 4KHz. Furthermore, the THD is less than 0.24% at 4 KHz in both simulation and experimental results.

In this thesis, a brand new first-order low pass square root domain filter (SRD filter) based on operational transconductors amplifiers (OTAs) is presented. The SRD filter consists of a translinear filter and two OTAs. We improve Cruz¡¦s SRD filter [15], reduce the number of transconductors from 3 to 2, and replace Class-AB linear transconductors with OTAs. The circuit has the least number of transistors up to date, therefore, the least power consumption and least chip area. The circuit has been fabricated with 0.35£gm CMOS technology. It operates with a supply voltage 1.5V and the biasing current varies from 0.05uA to 15uA. Measurement results show that the cutoff frequency of the filter can be tuned from 250 Hz to 29 kHz when the external capacitance C is 1nF and the cutoff frequency can be tuned from 1.8 kHz to 237kHz when the external capacitance C is 100pF. The total harmonic distortion is 1.03% and 1.01% when the external capacitance C is 1nF and 100pF and the power consumption is 116£gW.

Semiconductor optical amplifiers (SOA) and electroabsorption modulators (EAM) have been become vital elements to obtain high-output-power and high-speed optical signal in the optical fiber communications. In this paper, we propose a novel type cascaded integrated SOAs and EAMs, which are monolithically integrated in the same chip without any regrowth. In the active region, high electron bandgap offset material, InGaAsP/InAlGaAs, is used in order to get high optical gain and also high modulation. Using cascaded SOAs and EAMs, high impedance of microwave stripe lines are the bridges connecting the small EAM elements, bring up higher impedance and thus enhancing the microwave transmission. The optical waveguide is made by selectively undercut etching InGaAsP/InAlGaAs material in order to reduce the optical scattering loss and also the microwave loss due to the low parasitic capacitance. The processing is described by the following steps: (1) ion implantation to get electrical isolation; (2) wet etching to form the optical waveguide ridge; (3) e-gun evaporation to get n- and p- metalization ; (4) spinning PMGI as planarization; (5)Final thick metalizations as for microwave transmission line. The final integrated cascaded SOAs and EAMs has been successfully fabricated and measured. In comparison with single EAM, higher than 10GHz of ¡V3dB electrical transmission has been found, indicating the cascaded integration structure has better impedance matching and also higher electrical transmission. The measured optical gain is higher than 5dB with 11dB/V modulation efficiency at excitation wavelength of 1568nm.

This dissertation presents a hybrid quadrature polar modulator (HQPM) to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter with good potential for multi-mode operation. For enhancing the efficiency, a Class-E PA is used in the transmitter. The HQPM consists of a quadrature modulator for processing the RF modulated carrier and a Class-S modulator for processing the supply-voltage signal. The quadrature modulator and the Class-S modulator deliver the output signals with envelope variation before being inserted into the RF-input terminal and the supply-voltage terminal of Class-E PA, respectively, causing the double envelope modulation to distort the modulated RF signal at the PA output. Therefore, a digital predistorter is proposed to be embedded in the HQPM for compensation. The use of such predistorted HQPM techniques can help reducing the average DC and RF input powers and the output feed-through levels so as to enhance power added efficiency and adjacent channel power rejection quite remarkably.

For millimeter wave applications, MMIC is the best contemporary technology. Considering the requirements of the commercial and military applications on amplitude and phase linearity, it is necessary to reduce the nonlinearity of the amplifiers. There are several linearization techniques that are used to reduce the nonlinearity effects. In the context of the thesis, a special analog predistortion technique that is called &ldquo / self cancellation scheme&rdquo / is used to linearize a 35GHz MMIC amplifier. The amplifier to be linearized is used in the design of the predistorter, that is why it is called self cancellation. This thesis contain the design of the amplifier, lumped element power divider and combiner circuits, and the complete analog predistortion linearizer. Layouts of linearizer system and its components are prepared and layout effects are taken into account.

Using GaAs HBT provided by AWSC to construct Gummel Poon static model.then using the GaAs HBT processing of GCS to design MMIC power amplifier for the 1.9~2.0 GHz PCS system. This power amplifier exhibits an output power of 27dBm and a power added efficiency as high as 32% at an operation voltage of 3.4V.

Three high performance circuits for a low power supply DRAM¡¦s are presented in this thesis. First, a modified multi-stage sense amplifier is proposed, that utilizes the auxiliary transmission gate and charge recycling technique. The auxiliary NMOS transistor of the multi-stage sense amplifier is replaced by the transmission gate to improve the sensing speed. In addition, the charge recycling technique is used to reduce the power dissipation of multi-stage sense amplifier. It improves the sensing time by 6.1ns (24.4%) compared to that of the conventional multi-stage sense amplifier and the power saving percentage of 25.6% compared to that of the conventional one. Second, an improved Standby Power Reduction (SPR) Circuit is reported. The capacitor boosting technique is utilized in our proposed Static Current Cut-off Standby Power Reduction (SCCSPR) Circuit, which turns off the always-on MOS transistor of SPR circuit. The power consumption is 30.9% reduced by our design compared to that of the conventional SPR circuit. Third, an improved voltage doubler is developed. The indirect switch is utilized in our proposed circuit, it provides larger gate source bias applied to the PMOS pass transistor. Thus, the current drivability is arisen and the pumping speed is improved as well. In the 2V supply voltage, the pumping speed of our modified voltage doubler is arisen about 18.6% compared to that of the conventional voltage doubler. These high performance circuits in this thesis are applied in a 1-Kbit DRAM circuits. A data access time of 36ns and total power consumption 52.58mW are attained when the supply voltage is 2V. The access time of 10.3ns (22.2%) and power consumption of 6.44mW (11%) are reduced compared to that of the conventional DRAM.