Techn. Hochsch., Diss., 1999--Aachen.

Due to the rapid growth of the communication market, a large amount of research is in process toward a high speed and high resolution sigma-delta A/D converter. This dissertation focuses on the design of a single-stage sigma-delta A/D converter with very low oversampling ratio for the wireless application. An architecture for a multibit single-stage delta-sigma A/D converter with two-step quantization is proposed. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine DEM and DAC is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise-shaped by using a digital requantization (REQ) algorithm. A second-order single-stage sigma-delta A/D converter with 8-bit two-step inner quantization is proposed in this dissertation, which employs the feed-forward branches to reduce the integrator output swing. The proposed modulator is implemented with TSMC 0.25 μm mixed-signal process, using the switched-capacitor circuit. The measured system achieves the dynamic range of 70 dB under an oversampling ratio of 16 with the REQ algorithm reducing the noise floor in the signal bandwidth by 20 dB.

Abstract The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs) has traditionally required test instruments with higher linearity and resolution than that of the device under test. In this thesis ways to test converters without expensive precision instruments are studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) and integral non-linearity (INL) estimation is proposed. The algorithm assumes that two stimuli with constant offset between them are applied to the ADC under test and that the code density histograms for both stimuli are recorded. The probability density function (PDF) of the stimulus is then solved using simple calculations so that DNL and INL of the ADC can be estimated without a priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputs are digital and the new algorithm can be used to obtain the PDF of the DAC output. Moreover, the PDF of DAC actually characterizes its INL and DNL so that this all-digital test configuration enables a simultaneous testing of both converters thanks to the new algorithm. The proposed algorithm is analyzed thoroughly both mathematically and by carrying out several simulations and experimental tests. On the basis of the analysis it is possible to approximate the impending estimation error and select the optimal value for the offset between the stimuli. In theory, the accuracy of the algorithm proposed equals that of the standard histogram method with ideal stimulus, but in practice, the accuracy is limited by that of the offset between the stimuli. Therefore, special attention is paid to development of an accurate and small offset generator which enables ratiometric test setup and solves the problems in the case of reference voltage drift. The proposed on-chip offset generator is built using only four resistors and switches. It occupies 122·22 μm2 in a 130 nm CMOS process and accuracy is appropriate for the INL testing of 12-bit converters from rail-to-rail. Based on the analysis of the influence of resistor non-linearity on the accuracy of offset, it is possible to improve the offset generator further. With discrete resistors, the INL of 16-bit ADCs was tested using a 12-bit signal generator. The proposed simple algorithm and tiny offset generator are considered to be important steps towards built-in DNL and INL testing of ADCs and DACs.

Auf dem Gebiet der Flugnavigation hat die Darstellung raumbezogener Information traditionell eine herausragende Bedeutung ...

Die vorliegende Arbeit beschreibt die Analyse und den Entwurf eines vollintegrierten Empfängers im UHF-Bereich mit dem Ziel, für die Verwendung im Mobilfunkstandard der vierten Generation geeignet zu sein, aber auch eine Einschätzung bezüglich der Anwendbarkeit eines solchen Empfängers für Geräte der fünften Generation vorzunehmen. Bei dem Empfängerkonzept handelt es sich um einen direkt digitalisierenden Empfänger, d.h. das Empfangssignal wird direkt mittels Analog-Digital-Umsetzer digitalisiert und vorher nicht auf eine niedrigere Trägerfrequenz abwärtsgemischt. Der Analogteil eines direkt digitalisierenden Empfängers besteht also nur aus einem LNA und einem ADU. Diese Empfängertopologie stellt hohe Anforderungen an den ADU und bildet deshalb den Fokus dieser Arbeit. Für die Untersuchungen des Empfängerkonzepts wurde sich auf eine Implementierung für niedrige Mobilfunkfrequenzbänder beschränkt, weshalb für den Entwurf festgelegt wurde, eine Trägerfrequenz von 750MHz mit einer Signalbandbreite von 20MHz empfangen und verarbeiten zu können. Der Entwurf erfolgte in einer 28nm CMOS Technologie, sollte flächen- und stromsparend sein, sich aber auch für zukünftige Technologieknoten mit noch höherer Integrationsdichte eignen, ohne die analogen Schaltblöcke gesondert bei der Technologiewahl berücksichtigen zu müssen. Somit konnten integrierte Spulen in der Empfängerkette nicht verwendet werden. Zugleich muss im Empfänger der Alias-Effekt unterdrückt werden. Um diese strengen Rahmenbedingungen ohne exorbitante Stromaufnahme zu erfüllen, kommt als ADU-Topologie nur ein zeitkontinuierlicher Sigma-Delta-Modulator in Frage. Dazu musste das Schleifenfilter des Sigma-Delta-Modulators komplett neu entworfen werden, was u.a. den Entwurf einer einstellbaren hochgütigen aktiven Spule erforderte. Das Empfängerkonzept konnte erfolgreich an der gefertigten Schaltung verifiziert werden, der gemessene dynamische Bereich blieb jedoch weit hinter dem ursprünglich anvisierten Ziel von 84dB zurück. Es konnte lediglich ein dynamischer Bereich von 59dB bei einer Leistungsaufnahme von 36,4mW und einer maximalen Auflösung von 4,5 Bit erreicht werden. Nachfolgende Untersuchungen des Konzepts zeigen aber Lösungsansätze auf, mit denen die Auflösung auf 8,7 Bit und der Dynamikbereich auf 69dB gesteigert werden kann.

Submitted by Filipe dos Santos (fsantos@pucsp.br) on 2017-03-24T11:46:32Z No. of bitstreams: 1 Natália Aly Menezes.pdf: 27946657 bytes, checksum: 8d1cea71afe08bfa99c2cd060e96f7be (MD5) / Made available in DSpace on 2017-03-24T11:46:32Z (GMT). No. of bitstreams: 1 Natália Aly Menezes.pdf: 27946657 bytes, checksum: 8d1cea71afe08bfa99c2cd060e96f7be (MD5) Previous issue date: 2017-03-13 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This research seeks to contextualize the experimental audiovisual practices of the present through a strong connection with the past. Thus, the thesis excavates the earliest sources of optical and acoustic investigations that have, over the years, resulted in machines and media that surround us nowadays. However, the research does not follow linearities of traditional history. The theoretical methodology of the media archaeology is used seeking to restructures the mediatic historicism. Therefore, it’s possible to make analogies between alchemical practices (methods and discoveries), and the audiovisual contemporary practices. Moreover, this research aims to approach past and present in a technical way, in the union and combination of analog and digital, proposing an analysis and the creation of fruitful hybrid structures of the experimental audiovisual / Esta pesquisa busca contextualizar as práticas audiovisuais experimentais do presente a partir de uma forte ligação com o passado. Para tanto, escava as mais antigas fontes de investigações óticas e acústicas que resultaram, ao logo dos anos, máquinas e mídias que nos cercam atualmente. No entanto, a pesquisa não segue linearidades da história tradicional. É usada a metodologia teórica da arqueologia das mídias que justamente reestrutura o historicismo midiático. Assim, é possível fazer analogias entre, por exemplo, práticas alquímicas – seus métodos e descobertas – para colocar em paralelo com os traquejos do audiovisual. Da mesma forma, esta pesquisa busca unir passado e presente de forma técnica, na união e combinação de estruturas maquínicas analógicas e o digital, propondo a criação e análise das frutíferas estruturas híbridas do audiovisual experimental

<p>The report descripbs how a diplexer for a hybrid analog/digital filterbank has been constructed and tested. A diplexer divides the frequency band into two different bands that do not who doesn't overlapp each other. The sampling rate for the two ADC:s is 80 Msps, and therefore it is advantage to have zero at 80 MHz. The reason for this is that a proposed class of hybrid filterbanks with very good quality requires a zero at or close the sampling frequency to work well. </p><p>The diplexer was made in three versions. The first didn't work since the choosen inductance self resonance frequency was to low and by the same range as the filters bandwidth. The second version had to much losses, which resulted in attenuation at 80 MHz, which was to small. The third version was made in two differents layout. </p><p>To the diplexer it was also made a test tool in Labview, through that one gets the magnitude ande phase functions. </p><p>The results show that the magnitude function is good for version 3.0 and for version 3.1, and that the losses are low. It depends also on that the choosen components have a high self resonance frequency. There can't been shown any differences between these two, thus is is difficult to judge if one is better then an other.</p>

The report descripbs how a diplexer for a hybrid analog/digital filterbank has been constructed and tested. A diplexer divides the frequency band into two different bands that do not who doesn't overlapp each other. The sampling rate for the two ADC:s is 80 Msps, and therefore it is advantage to have zero at 80 MHz. The reason for this is that a proposed class of hybrid filterbanks with very good quality requires a zero at or close the sampling frequency to work well. The diplexer was made in three versions. The first didn't work since the choosen inductance self resonance frequency was to low and by the same range as the filters bandwidth. The second version had to much losses, which resulted in attenuation at 80 MHz, which was to small. The third version was made in two differents layout. To the diplexer it was also made a test tool in Labview, through that one gets the magnitude ande phase functions. The results show that the magnitude function is good for version 3.0 and for version 3.1, and that the losses are low. It depends also on that the choosen components have a high self resonance frequency. There can't been shown any differences between these two, thus is is difficult to judge if one is better then an other.

In diesem Beitrag wird eine Methode zur Beschreibung von Kostenfaktoren und deren Verknüpfung über Hierarchiegrenzen hinweg dargestellt. Sie eignet sich sowohl für rein digitale Systeme mit Softwareanteilen als auch für gemischt analog/digitale Systeme. Damit ist sie im Hardware-Software Codesign und im Analog-Digital Codesign zum Vergleich verschiedener Systemkompositionen anwendbar. Die Implementierung mit C++ ermöglicht neben einer Nutzung mit digitalem SystemC auch den Einsatz mit der analogen SystemC-Erweiterung SystemC-AMS und vereinfacht die Nutzung gegenüber einer vorhandenen VHDL-Implementierung. Als Anwendungsbeispiel fungieren Komponenten eines Systems zur Inertialnavigation.

Due to the prevalence of pulse encoders for system state information, an all-digital proportional-integral-derivative (ADPID) is proposed as an alternative to traditional analog and digital PID controllers. The basic concept of an ADPID stems from the use of pulse-width-modulation (PWM) control signals for continuous-time dynamical systems, in that the controllers proportional, integral and derivative actions are converted into pulses by means of standard up-down digital counters and other digital logic devices. An ADPID eliminates the need for analog-digital and digital-analog conversion, which can be costly and may introduce error and delay into the system. In the proposed ADPID, the unaltered output from a pulse encoder attached to the systems output can be interpreted directly. After defining a pulse train to represent the desired output of the encoder, an error signal is formed then processed by the ADPID. The resulting ADPID output or control signal is in PWM format, and can be fed directly into the target system without digital-to-analog conversion. In addition to proposing an architecture for the ADPID, rules are presented to enable control engineers to design ADPIDs for a variety of applications.