This thesis addresses a game design matter with an interaction design perspective, arguing that both are strongly related and can learn from each other. It explores the topic of designing mechanics for asymmetric cooperation in hybrid social co-located games. Co-located social games are games played in a same space, and hybrid games merge analog and digital features. When dealing with asymmetric cooperation mechanics, players work together towards the same goal but with different mechanics (different ability to act or to access to information). Cooperation is more and more popular in the game field and, among with other benefices, asymmetry can strengthen it by making the performances of the players fully complementary. In hybrid games, this kind of mechanics could make people bridge the gap between physical and digital materials through cooperation, by combining actions or sharing information. Following a theoretical investigation on the matter, this paper presents several experiments of asymmetric cooperation mechanics involving digital aspects thanks to a smartphone, and sparking strong social interactions. A discussion is drawn upon them to share the resulting observations on hybrid asymmetric cooperation and on the process of prototyping game mechanics.

The digital transformation of production and living is one research field with potential to overcome arising ecological and social problems. Digital technologies associated with the internet of things (IoT) enable new intelligent, sustainable and efficient production techniques. Massive monitoring and optimal controlling of industrial processes (smart fabrication) and human living (smart cities) ultimately results in the reduction of resource demands. Key parts of these new applications are microelectronic sensor read-out systems connected in IoT sensor networks, which measure and transmit multi-physical environmental parameters. In practical applications, large quantities (tens to hundreds) of sensor nodes are used. Circuitry with minimized power consumption is necessary to ensure long operation time and low maintenance cost. The motivation of this work is the development of a low-power, low-cost, microelectronic sensor read-out circuit, which combines flexibility of employed IoT sensor hardware with flexibility in complementary metal oxide semiconductor (CMOS) technology. This work covers design and implementation of an integrated multi-sensor analog frontend (AFE) with a near-zero power consumption below 10 μW, which offers above-state of the art, real-time configurability of key parameters and flexibility in application and technology. It aims for IoT environmental sensing applications, where energy-efficient, medium-speed and medium-resolution data acquisition of different environmental sensor signals is required. Its innovative architecture supports a wide variety of voltage ranges, frequency levels and sensor types, while maintaining energy-efficiency in different operation modes. Samples of the developed AFE are employed in autonomous sensor nodes for smart cities and smart factories, where they collect and process environmental parameters such as weather (light, temperature) and gases. The durable sensor nodes are operated by energy harvester sources and transmit data wirelessly, demonstrating one practical realization of an autonomous zero-power IoT network. Moreover, the technological flexibility of the AFE is investigated by migrating one key building block, which is the analog-to-digital converter, to different CMOS technologies. Conclusions for the optimal CMOS node for the entire AFE are drawn by performance comparison. / Die digitale Transformation von Industrie und Gesellschaft hat das Potential, zur Bewältigung bevorstehender ökologischer und sozialer Krisen beizutragen. Moderne digitale Technologien, wie das Internet der Dinge (engl. internet of things, IoT), ermöglichen intelligente Produktionsketten von nie dagewesener Effizienz und Nachhaltigkeit. Mit feingranularer Kontrolle und optimierter Steuerung soll schlussendlich der Ressourcenverbrauch von geregelten Prozessen, zum Beispiel in der smarten Fabrik und in der smarten Stadt, verringert werden. Schlüsseltechnologien dieser neuen Anwendungsfälle sind mikroelektronische Sensor-Auslese-Schaltungen, die multi-physikalische Umweltparameter messen und drahtlos in IoT-Netzwerke übertragen. In praktisch relevanten Szenarien bestehen solche Netzwerke aus dutzenden bis tausenden Sensorknoten. Unter unternehmerischen Gesichtspunkten sind lange Betriebszeiten ohne Batteriewechsel und geringe Wartungskosten notwendig, welche u. a. durch Elektronik mit minimalem Energieverbrauch erreicht werden können. Die Motivation dieser Arbeit ist die Entwicklung einer energiesparenden und kostengünstigen mikroelektronischen Sensor-Auslese-Schaltung, die Flexibilität in der Auswahl der eingesetzten IoTSensoren mit Flexibilität in der Auswahl der Halbleiter-Technologie (engl. complementary metal oxide semiconductor, CMOS) verbindet. Diese Arbeit behandelt Entwurf und Implementierung eines integrierten Multi-Sensor-Analog-Frontends (AFE) mit extrem geringer Leistungsaufnahme von weniger als 10 μW (engl. near zero power), dessen Echtzeit-Konfigurierbarkeit von relevanten Parametern und dessen Flexibilität in Anwendung und Technologie ein Niveau erreicht, das sich über dem Stand der Technik befindet. Es soll in IoT-Anwendungen eingesetzt werden, in denen die energieeffiziente Verarbeitung von verschiedenen Umwelt-Sensor-Signalen mit mittlerer Geschwindigkeit und mittlerer Genauigkeit gefordert ist. Mit seiner innovativen Architektur unterstützt es einen großen Bereich von Eingangsspannungen, Eingangs-Frequenzen und Sensor-Typen in unterschiedlichen Operations-Modi, wobei seine Energieeffizienz nicht beeinträchtigt wird. Exemplare des entworfenen AFEs werden durch den Einsatz in autonomen Sensorknoten für die smarte Stadt und die smarte Fabrik, wo sie Umweltparameter wie Wetter (Licht, Temperatur) und Gaskonzentrationen sammeln und verarbeiten, in die Anwendung überführt. Die langlebigen Sensorknoten, die ihre Energie von alternativen Quellen beziehen und via drahtloser Funkverbindung kommunizieren, demonstrieren eine praktische Realisierung eines autonomen Zero-Power-IoT Netzwerkes. Zusätzlich untersucht diese Arbeit die Technologie-Flexbilität des AFEs, indem ein Kernbaustein, der Analog-Digital-Wandler, in verschiedene CMOS-Technologien migriert wird. Anhand eines Vergleichs werden Schlüsse für den optimalen Technologieknoten des gesamten AFEs gezogen.

In order to improve the sensitivity of an optical receiver, the gain and the collection area of the photo-detectors within the receiver should be increased. Detectors with internal gain such as avalanche photodiodes (APD) are usually used to increase the sensitivity of the receiver. One problem with APDs is the sensitivity of their gain to their bias voltage, which makes them challenging to be fabricated in a standard CMOS process due to variations in their gain. However, when an APD is biased over its breakdown voltage, it is sensitive to a single photon, hence, referred to as a single photon avalanche diodes (SPAD). The SPADs are photon-counting detectors, which are less sensitive to their bias voltage, and can be integrated with rest of the electronic circuitry that form an optical receiver. An avalanche diode requires dedicated circuits to be operated in the SPAD mode. These circuits make the diode insensitive to an incident photon for a duration that is known as deadtime. Unfortunately, The collection area of the PD, APD, and SPADs are limited to their capacitance. Hence, a large photo-detector leads to a larger capacitance, which reduces the bandwidth of the receiver. In this thesis, a photon counting optical receiver based on an array of SPADs is proposed which increases the collection area with a low output capacitance. The avalanche diode and peripheral circuits which operate and readout-out the SPAD array are fabricated in the commercially available UMC 0.18 μm CMOS process. Initially, the avalanche diode is tested and characterised. A high performance circuit is then designed and tested which is able to achieve short deadtimes up to 4 ns. Once the photon counting operation of the SPAD is verified, a numerical model is developed to investigate the influence of several factors, including the deadtime, on the performance of the photon-counting detector in a communication link. Based on the simulation results, which show the advantages of an array over a single detector, a prototype detector array of 64 asynchronous SPADs is designed and tested. This array uses a high-speed readout mechanism which is inspired by the current steering digital-to-analogue converters. Bit error ratio tests (BERT) verify the photon counting capability of the proposed detector, and a bit error rate of 1E-3 has been achieved at data rate of 100 Mbps. In addition, the array of SPAD is compatible with a front-end of conventional optical receiver which uses a photodiode as a photo detector.

L'exploration du système solaire et l'étude de l'univers lointain sont encore sources de découvertes et de mystère pour la communauté scientifique et pour l’humanité en général. Ces observations sont actuellement principalement basées sur la mesure d’ions et de particules in-situ qui constituent ces milieux. Les instruments d’observation intègrent des détecteurs spatiaux, utilisés pour convertir l'énergie des particules en charges électriques mesurables. Ces derniers sont étroitement liés à leur électronique analogique ou Analog-Front-End (AFE) et cette combinaison forme des chaines astrophysiques de détection appelées « sensor heads ». Depuis quelques années, la volonté d’améliorer les résolutions spatiale et spectrale des détecteurs nécessite la conception d’une électronique intégrée multivoies. Ainsi, une électronique spatiale de type Application Specific Integrated Circuit (ASIC) doit être développée. Cela permet d’une part de s’adapter au mieux à chaque détecteur pour en optimiser les performances ; et d’autre part de bénéficier des multiples avantages inhérents à l’utilisation d’une technologie CMOS : diminuer les dimensions et les temps de transit des signaux, intégration multifonctions, réduction des coûts pour une fabrication de masse et effets parasites étudiés et bien connus. Cependant les contraintes spatiales exigent une qualification draconienne du circuit. En effet, ces environnent radiatifs peuvent endommager les systèmes électroniques embarqués à bord des missions spatiales. Grâce à la réduction des dimensions, il ne semble plus opportun aujourd’hui d’utiliser des technologies dédiées au spatial (type SOI ou biCMOS spécifiques) mais plutôt de mettre en œuvre des techniques de durcissement par design (RHBD) sur des technologies standards qui sont moins onéreuses et plus performantes. L’objectif de cette thèse est la conception de nouvelles chaînes d’instrumentations intégrées multivoies pour le spatial. Ce travail, co-financé par le CNES et le CNRS, s’est inscrit dans le cadre d’un projet soutenu par le Réseau Thématique de Recherche Avancée Sciences et Technologies pour l’Aéronautique et l’Espace (RTRA STAE) entre 2008 et 2011, intitulé CASA (Chaines AStrophysiques et leur instrumentation Associée). Au cours de cette thèse nous avons conçu 2 ASICs associés à 2 types de détecteurs spatiaux bien distincts. Le premier permet de compter les électrons en sortie d’une microchannel plate (MCP) tandis que le deuxième permet de quantifier le niveau d’énergie perdu par les e- en pénétrant dans un SC. L’étude de ces différents détecteurs doit d’abord être faite afin de les modéliser pour une parfaite adéquation avec leur électronique de détection. Ensuite, une optimisation des chaînes de conversion en vitesse, bruit et consommation est réalisée. Enfin, une méthodologie de savoir faire au niveau du traitement des informations doit être développée pour pérenniser l’expérience emmagasinée durant ces travaux. / The solar system exploration and study of the distant universe are still sources of discovery and mystery to the scientific community and for humanity in general. These observations are currently mainly based on the measurement of ions and particles in-situ forming these environments. The observation instruments incorporate spatial sensors, used to convert particles energy into electrical charges measurable. These are closely related to their electronic analog or Analog-Front-End (AFE) and the combination form chains astrophysical detection called "sensor heads". In recent years, the desire to improve the spatial and spectral resolution detectors requires the design of a multichannel integrated electronics. Thus, a spatial-type electronic Application Specific Integrated Circuit (ASIC) should be developed. This allows one hand to best adapt to each detector to optimize performance, and on the other hand to benefit from multiples advantages inherent in the use of CMOS technology: reducing the size and transit time signals, multi-function integration, cost reduction for mass production and interference effects studied and well known. However, the spatial constraints require a drastic qualification of the circuit. Indeed, the surrounding radiation can damage electronic systems on board the space missions. By reducing the size, it seems more appropriate today to use technologies for the space (or BiCMOS SOI specific) but rather to implement hardening design techniques (RHBD) on standard technologies that are less expensive and more efficient. The objective of this thesis is the design of new integrated multi-channel instrumentation for space. This work, co-funded by CNES and CNRS, has registered as part of a project supported by the Advanced Research Thematic Network Science and Technology for Aeronautics and Space (RTRA STAE) between 2008 and 2011, called CASA (Channels Astrophysics and their associated instrumentation). In this thesis we have designed two ASICs associated with two types of distinct space detectors. The first is used to count the electrons at the output of a MicroChannel Plate (MCP) and the second quantifies the amount of energy lost by e- by entering in a SC. The study of these different sensors must first be made to model them for a perfect match with their detection electronics. Then the chain optimization in conversion speed, noise and consumption is achieved. Finally, a methodology of knowledge in the processing of information must be developed to sustain the experience stored in this work.

Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted. A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region. The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell. Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.

Orientador: Frab Norberto Bóscolo / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Odontologia de Piracicaba / Made available in DSpace on 2018-08-22T13:39:06Z (GMT). No. of bitstreams: 1 Frazao_MarcoAntonioGomes_D.pdf: 4262109 bytes, checksum: 0e3256f8a0dd02738990d526d5a2329b (MD5) Previous issue date: 2012 / Resumo: Com este estudo, teve-se a proposta de avaliar a modificação da densidade de 4 cores (branco, cinza claro, cinza escuro e preto) em filmes radiográficos impressos por duas tecnologias dry seca: termográfica (AGFA) e fototermográfica (KODAK). Para isso, foi utilizada uma amostra formada por 18 grupos com 6 corpos de prova para cada uma das tecnologias de impressão totalizando um experimento com 216 corpos de prova submetidos às temperaturas de 40ºC, 60ºC e 80ºC, pelos tempos de 30, 60 e 120 minutos com e sem a exposição solar. Nestes foram realizadas analises densitométricas antes e depois da exposição aos fatores estudados e os dados obtidos submetidos aos testes estatísticos de: Kruskal Wallis, Mann-Whitney e Wilcoxon para dados pareados com nível de significância de 5%. Pôde-se observar que as cores avaliadas impressas no filme pela tecnologia termográfica (AGFA) modificam sua densidade a partir de combinações de exposição a 60ºC e 120 minutos e a 80ºC e 30 minutos sem a exposição ao sol e a partir de 40ºC e 30 minutos com exposição solar, e no filme impresso pela tecnologia fototermográfica (KODAK) modifica sua densidade a 40ºC a partir de 30 minutos com e sem a exposição solar. Concluiu-se que o aumento da temperatura de armazenamento bem com a exposição à luz solar modificam a densidade dos filmes radiográficos impressos pelas tecnologias dry seca avaliadas / Abstract: The purpose of this study was to evaluate the density modification of 4 colors (white, light gray, dark gray and black) in films printed by two dry technologies: thermographic (AGFA) and photothermographic (KODAK). A sample consisting of 18 groups with six specimens per printing technologies was used, totaling an experiment of 216 evaluated specimens when subjected to temperatures of 40°C, 60°C and 80°C, for periods of 30, 60 and 120 minutes with and without sunlight exposure. These specimens were submitted to densitometric analysis before and after exposure to the studied factors and data were subjected to the following statistical tests: Kruskal Wallis, Mann-Whitney and Wilcoxon for paired data. It was observed that the evaluated colors printed on the film by thermographic technology (AGFA) modify their density at exposures to 60°C and 120 minutes, and without sunlight exposure at the temperature of 80°C after 30 minutes, and with sunlight exposure from 40°C and 30 minutes, and the film printed by photothermographic technology (KODAK) modifies its density at 40°C from 30 minutes with and without sunlight exposure. It was concluded that the increase of storage temperature and sunlight exposure modify the density of radiographic films printed by dry technologies / Doutorado / Radiologia Odontologica / Doutor em Radiologia Odontológica

In diesem Beitrag wird eine Methode zur Beschreibung von Kostenfaktoren und deren Verknüpfung über Hierarchiegrenzen hinweg dargestellt. Sie eignet sich sowohl für rein digitale Systeme mit Softwareanteilen als auch für gemischt analog/digitale Systeme. Damit ist sie im Hardware-Software Codesign und im Analog-Digital Codesign zum Vergleich verschiedener Systemkompositionen anwendbar. Die Implementierung mit C++ ermöglicht neben einer Nutzung mit digitalem SystemC auch den Einsatz mit der analogen SystemC-Erweiterung SystemC-AMS und vereinfacht die Nutzung gegenüber einer vorhandenen VHDL-Implementierung. Als Anwendungsbeispiel fungieren Komponenten eines Systems zur Inertialnavigation.

Die vorliegende Arbeit behandelt den Entwurf eines ADCs nach dem sukzessiven Approximationsverfahren (SAR). Ausgehend von den Systemanforderungen erfolgt eine Ableitung der Spezifikation des zu entwerfenden ADCs. Theoretische Betrachtungen und Highlevelsimulationen in Matlab wählen die optimale Architektur der Einzelkomponenten - kapazitives DAC Array, Komparator, Ablaufsteuerung - aus. Die Implementation selbst findet für die Analogschaltungsteile auf Transistorebene und für die digitalen Komponenten auf RT-Ebene in VHDL statt. Sie bilden die Grundlage für die Realisierung des Layouts. In dem Zusammenhang stellt die Arbeit die gängigsten Matchingmethoden für elektronische Bauelemente vor. Abschließende PEX-Simulationen (parasitic Extraction) ermitteln die statischen (INL/DNL) wie dynamischen Kennwerte (SNR) des SAR-ADCs.:Abkürzungsverzeichnis iii Formelzeichen v 1 Einleitung 1 2 Grundlagen 2 2.1 Analog/Digital-Umsetzer 2 2.1.1 Umsetzungsverfahren 2 2.1.2 Statische Kennwerte 8 2.1.3 Dynamische Kennwerte 12 2.2 Technologie 17 2.2.1 Übersicht 17 2.2.2 MOS-Transistoren 17 2.2.3 Kapazitäten 18 2.2.4 Widerstände 18 2.3 Hardwarebeschreibungssprache 19 2.3.1 Übersicht 19 2.3.2 Zustandsautomat 19 2.3.3 Look-Ahead-Ausgang 20 3 Spezifikation 21 4 ADU-Topologie 23 4.1 Vorüberlegungen 23 4.1.1 Umsetzungsverfahren 23 4.1.2 Vergleich Widerstand/Kapazität 23 4.1.3 Differenziell Vs. Single-Ended 24 4.1.4 Kapazitätsarray 25 4.2 ADC High-Level Modell 30 4.2.1 Funktionsblöcke 30 4.2.2 Matlab/Simulink 31 4.2.3 Simulation 34 4.3 Parasitäre Effekte 37 4.3.1 Substratkapazität 37 4.3.2 Komparatoroffset 39 5 Schaltungsdesign & -simulation 41 5.1 Komparator 41 5.1.1 Spezifikation 41 5.1.2 Latch 41 5.1.3 Vorverstärker 43 5.1.4 Gesamtsystem 46 5.2 Schalter 46 5.2.1 Funktionsweise 46 5.2.2 Ladungseintrag 46 5.2.3 Dimensionierung & Simulation 47 5.3 Kapazitätsarray 51 5.4 SAR-Controller 51 5.4.1 Vorüberlegung 51 5.4.2 RTL Design 52 5.4.3 Simulation 55 5.4.4 Synthese 57 5.4.5 Optimierung 59 5.5 ADC (Toplevel) 59 5.5.1 Architektur 59 5.5.2 Simulation 61 6 Layout 64 6.1 Komparator 65 6.1.1 Vorverstärker 1 65 6.1.2 Vorverstärker 2 66 6.1.3 Dynamisches Latch 66 6.2 Transmission Gates 67 6.3 Kapazitätsarray 68 6.4 SAR-Controller 70 6.5 ADC (Toplevel) 70 6.6 PEX Simulation 72 6.6.1 Statischer Test 72 6.6.2 Dynamischer Test 73 7 Zusammenfassung 74 Literaturverzeichnis 76 Bücher 76 Skripte und Schriften 76 Internetlinks 78 Abbildungsverzeichnis 79 Tabellenverzeichnis 82 Anhang 84

In my master thesis I realize the set of pictures and painterly objects, which should imitate principles of augmented reality by analogial form. From technical standpoint Im interested in question of bidirectional remediation of new media and painting and how its evolution supports ilussion and imagination. In ontologiacal way im looking for mystical nature of picture. Final exhibition is an metaphor composed in hybryd picture based on technological and theoretical experiences in Painting. The result is little synthetic reality.

The aim of the workshop is to present and discuss several ideas which relate to technology as well as to creative teaching. Educational experience, common sense and educational research have all proven how important for comprehensive understanding different cognitive representations are. We will present and discuss several elementary mathematical ideas of which mechanical realisations mean ingenius technological inventions (for example: ‘car differential’ and ‘digital sound technology’). Technological insights can provide deep intuitive understanding of otherwise abstract mathematical concepts and therefore yield also better comprehension of mathematics. Besides that we will use and present the technology in the form of dynamic geometry programs to show, provoke and motivate rethinking and deeper understanding of several elementary mathematical concepts.