Conventionally, the performances of Analog and Mixed-Signal (AMS) circuits have been characterized using specification-based functional tests. In these test methods, the correct functionalities of AMS circuits are verified by measuring pre-determined specification parameters of AMS circuits. The conventional test methods provide accurate test results by using various test equipments which generate functional test signals and capture the test responses externally. However, due to rapid increase in the performance of AMS circuits in recent years, the conventional test methods face various challenges in the aspects of test cost, test time and testability. The goal of this dissertation is to develop innovative functional test methods for AMS circuits which are aimed at reducing the test cost and test time while providing comparable test accuracy to the conventional test methods. To achieve this goal, efforts have been made to explore the characteristics of AMS circuits in a system level and to research efficient performance characterization methods based on the system level modeling of Devices Under Test (DUTs). As a part of these efforts, the pseudorandom test methods for nonlinear AMS circuits have been developed. In these methods, the pseudorandom signal is used to excite the DUT and to generate the test response which has sufficient information to characterize DUT performances. The pseudorandom test methods use the Volterra series model to capture the nonlinear behaviors of AMS circuits and to calculate various specification parameters of the DUT using the pseudorandom test response. In doing so, the performances of nonlinear AMS circuits can be characterized straightforwardly and accurately using a low-cost test setup. Also, in an effort to reduce the test time, parallel test methods of AMS circuits have been developed in which multiple DUTs are tested simultaneously by sharing a common test setup. In these methods, the test responses generated from different DUTs are combined together and the resulting composite test response is used to characterize the performance of each DUT individually. This will reduce the use of tester resources and will increase the test throughput beyond the level limited by the test equipments. The spectral characteristics of test stimulus are studied along with the system level behavior of AMS circuits to develop the efficient parallel test methods. Finally, in order to consider the practical issue of generating at-speed test stimuli for high-speed DUTs using a low-cost test setup, a reconfigurable built-off test interface is developed which can be used to generate various test patterns, including high-speed pseudorandom signal, using a low-speed tester. / text

Thesis (Ph. D.)--University of Washington, 1998. / Includes bibliographical references (leaves [152]-159).

Le développement croissant de systèmes embarqués de consommation, où les composants numériques, analogiques et logiciels sont combinés sur une même puce, résulte en une augmentation de la complexité des processus de conception et de vérification. La validation de tels systèmes analogiques et à signaux-mixtes reste largement basée sur des techniques de simulation, qui sont souvent combinées avec des méthodes d'analyse de nature ad-hoc. Cette thèse est motivée par l'exportation de méthodes formelles basées sur des propriétés, vers leur application à la validation de systèmes analogiques et à signaux mixtes, considérés à leur niveaux d'abstraction continu et temporisé.<br />Etant-donné que la vérification formelle de systèmes continus non-triviaux reste très difficile, nous nous tournons vers une méthode de validation plus légère appelée le monitoring basé sur des propriétés. Nous définissons signal temporal logic STL comme langage de spécification de haut niveau qui permet d'exprimer des propriétés temporelles de signaux continus et temporisés. STL est une extension de la logique de temps-réel metric interval temporal logic MITL, où les signaux continus sont transformés en signaux Booléens avec des prédicats numériques, et les relations temporelles entre ces signaux son exprimées avec les opérateurs temporels habituels dont les propositions atomiques correspondent à ces prédicats. Nous développons deux procédures de monitoring, une offline et une incrémantale, qui permettent de vérifier si les traces de simulations sont correctes par rapport aux propriétés STL. Les deux procédures sont implantées en outil de monitoring analogique AMT. Notre approche de monitoring basé sur des propriétés est appliquée, en utilisant AMT, à deux études de cas réalistes, où nous étudions des propriétés d'une mémoire de type FLASH et d'une interface de mémoire DDR2. <br />Nous considérons aussi le problème de vérification formelle de systèmes temporisés, et développons une traduction modulaire des formules MITL avec les opérateurs futurs et passés, vers des automates temporisés. La construction que nous proposons est basée sur les testeurs temporels, une classe spécifique d'automates avec les entrées et les sorties qui réalisent la fonction séquentielle définie par la sémantique des opérateurs MITL. Nous montrons d'abord comment chaque formule MITL peut être exprimée avec six opérateurs basiques (trois opérateurs passés et trois futurs) et nous proposons une construction de testeurs temporels à partir de ces opérateurs. Les testeurs temporels pour des formules MITL arbitraires sont obtenus en composant ces testeurs élémentaires.<br />Finalement, nous développons une procédure pour la synthèse automatique de contrôleurs à partir des spécifications de haut niveau exprimées avec le fragment borné de metric temporal logic (MTL). Nous proposons une traduction des propriétés spécifiées dans cette logique temporisée vers des automates temporisés déterministes, en supposant la variabilité bornée. Ensuite, nous pouvons appliquer à ces automates les algorithmes habituels de synthèse de sûreté pour construire un contrôleur qui satisfait la spécification par construction.

Parmi les produits électroniques de l’industrie des semi-conducteurs, les applications mixtes numériques-analogiques (AMS) représentent une part de marché à forte croissance. Le principal problème pour la conception de systèmes AMS est l’absence de flot de conception standard, puisque les blocs AMS ne peuvent pas être synthétisés de façon systématique `a partir d’une spécification de haut niveau en l’absence d’information au niveau transistor. Par ailleurs, il est très difficile de modéliser les caractéristiques au niveau transistor dans des descriptions comportementales de plus haut niveau (système). Face à ces d´défis, nous proposons une plateforme de modélisation, de dimensionnement et de vérification unifiée. La plate-forme repose sur une méthode de dimensionnement ascendant des blocs analogiques et une approche de simulation descendante depuis le système jusqu’aux transistors. Les différents niveaux d’abstraction envisagés sont d´écrits grâce aux langages C/C ++ et SystemC-AMS. En outre, nous expliquons comment UVM-SystemC-AMS développé dans le cadre du projet européen FP7 VERDI, fournit une m´méthode pour la vérification des systèmes AMS avec des interactions HW / SW. Nous appliquons ces méthodes à deux circuits. Le premier est un circuit de conversion analogique numérique pipeline à 3 étages et 6 bits. Il présente une vue hiérarchique du processus de conception. Le second est un sous-système analogique d’un système implantable de télémétrie, qui inclut une boucle de rétroaction. / Mixed-signal applications are among the fastest growing market segments in the electronics and semiconductor industry. This is driven by the growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, and security applications, which all require analog and mixed-signal (AMS) content. One bottleneck exists if the designs include analog components together with digital ones. Digital design has a well-defined, top-down design methodology, but AMS design has traditionally been an ad hoc custom design process, it is more time-consuming interactive process and fully based on designerÕs expertise. The major difficulty is how to model the impact of circuit non-idealities and technology process variations on system- level performances.In this thesis, we present an unified modeling, design and verification platform with a fast sizing and biasing methodology. The proposed methodology propagates the circuit-level non- idealities into system-level simulations in a very natural way. The methodology synchronizes SystemC-AMS TDF MoC and electrical circuit simulator (SPICE), which enables to mix non- conservative system-level model with conservative nonlinear circuit netlist. Besides, we explain how UVM-SystemC-AMS developed in the FP7 Verdi project, provides an unified methodology for the verification of systems having interconnected AMS, HW/SW. In order to explore the effectiveness of the proposed methodology, two case studies are investigated: a 3-stage 6-bit ADC pipeline and a voltage regulator for an implantable telemetric system. The problem of hierarchical design is illustrated in the 3-stage 6-bit ADC pipeline while the problem of system architecture with feedback loop is illustrated in the implantable telemetric system.

No description available.

The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal designs can be formally modeled as hybrid systems and therefore techniques used for formal analysis and verification of hybrid systems can be applied to the analog and mixed signal designs. Generally, formal verification tools for hybrid systems work at the abstract level where we model the systems in terms of differential equations or algebraic equations. However the analog and mixed signal system designers are very comfortable in designing the circuits at the transistor level. To bridge the gap between abstraction level verification and the designs validation which has been implemented at the transistor level, the very important issue we need to address is: Can we formally verify the circuits at the transistor level itself? For this we have proposed a framework for doing the formal verification of analog and mixed signal designs using SPICE simulation traces in one of the hybrid systems formal verification tools (i.e. Checkmate from CMU). An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design to be also used for validating its different refinements and design implementation, thereby providing a simple route to formal verification at different levels of implementation. Our approach has been illustrated through the case studies using simulation traces form the different frameworks i.e. Simulink/Stateflow framework and the SPICE simulation traces. We demonstrate the feasibility of our approach around the Checkmate and the case studies for hybrid systems and the analog and mixed signal designs.

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies.

Made available in DSpace on 2014-06-11T19:30:32Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-11-25Bitstream added on 2014-06-13T21:01:20Z : No. of bitstreams: 1 oliveira_vjs_dr_ilha.pdf: 2584742 bytes, checksum: ae7b3113a196a5051a808dbb371dece4 (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... / In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture

Orientador: Nobuo Oki / Banca: Suely Cunha Amaro Mantovani / Banca: Jozué Vieira Filho / Banca: Marcelo Arturo Jara Perez / Banca: Paulo Augusto Dal fabbro / Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture / Doutor

Cette thèse s’inscrit dans le domaine de la localisation de défauts de type «soft» dans les Circuits Intégrés (CI) analogiques et mixtes à l’aide des techniques dynamiques de stimulation laser en faible perturbation. Les résultats obtenus à l’aide de ces techniques sont très complexes à analyser dans le cas des CI analogiques et mixtes. Ce travail porte ainsi particulièrement sur le développement d’une méthodologie facilitant l’analyse des cartographies laser. Cette méthodologie est basée sur la comparaison de résultats de simulations électriques de l’interaction faisceau laser-CI avec des résultats expérimentaux (cartographies laser). L’influence des phénomènes thermique et photoélectrique sur les CI (niveau transistor) a été modélisée et simulée. La méthodologie a été validée tout d’abord sur des structures de tests simples avant d’être utilisée sur des CI complexes que l’on trouve dans le commerce. / This thesis deals with Soft failure localization in the analog and mixed mode Integrated Circuits (ICs) by means of Dynamic Laser Stimulation techniques (DLS). The results obtained using these techniques are very complex to analyze in the case of analog and mixed ICs. In this work we develop a methodology which facilitates the analysis of the laser mapping. This methodology consists on combining the experimental results (laser mapping) with the electrical simulations of laser stimulation impact on the device. The influence of photoelectric and thermal phenomena on the IC (transistor level) has been modeled and simulated. The methodology has been validated primarily on test structures before being used on complex Freescale ICs existing in commerce.